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Conexant
Conexant Systems
Description : 4-Channel Audio/Video Decoder with Integrated PCIe Interface

4-Channel Audio/Video Decoder with Integrated PCIe Interface

High Quality Audio and Video Decoders for Surveillance Applications
The CX25854 4-Channel Audio/Video Decoderwith Integrated PCIe Interface was designed for surveillance applications. The CX25854 contains four high quality NTSC/PAL video decoders with 10-bit A/Dsand 5-line comb filtering, to generate the highest quality digital video output with the lowest possible noise. This creates not only the best image quality for viewing, but enables lower bitrates for compression devices using the output of the CX25854.

Distinguishing Features
Four High-Quality NTSC/PAL video decoders:
– Anti-alias filters
– 10-bit A/Ds
– 5-line comb filtering
– Independent scaling
Four Mono audio A/Ds
– Variable sample rates
– I2S outputs
Flexible digital video output formats at 27, 54, and 108 MHz
– Byte-interleaved
– Line-interleaved
– Frame-interleaved (requires external DDR2 memory)
PCIe 1.1 x1 interface
Interface to Maxim CODECs for bridging of compressed data to PCIe
Tiling and cascading functions (requires external DDR2 memory)
Programmable Motion Detection
48 GPIO pins

Part Name(s) : W9970CF
Winbond
Winbond
Description : Video Graphics Controller

OVERVIEW
The W9970CF Integrated Video Graphics Accelerator is a highly integrated product offered by Winbond to provide high-performance graphical user interface (GUI) acceleration and TV-quality full-screen motion video acceleration for PCI Bus-based IBM PCs or their compatibles. An on-chip RAMDAC and dual programmable clock synthesizers with up to 135 MHz pixel data rate are also integrated to simplify system design and reduce cost.

FEATURES
❑ Integrated Video Graphics Controller
• 64-bit Graphics engine
• Integrated video accelerator
• On-chip 24-bit true color RAMDAC with up to 135 MHz pixel clock rate
• On-chip clock synthesizers generating up to 135 MHz VCLK and 80 MHz MCLK

Graphics Engine
• 64-bit Graphics acceleration
• 8/16/24 bit-per-pixel true color acceleration
• Deep command queue to improve GE performance
• Bit block transfer between system memory and display memory
   □  HostBLT
   □  Pattern BLT
   □  Color/font expanding BLT
   □  Transparent BLT
   □  Color/font expansion
   □  Rectangle fill
   □  256 three-operand (source, pattern and destination) ROPs
• Bresenham line drawing
• Short stroke vector drawing
• Rectangle and line clipping
• 64 x 64 x 2 or 32 ´ 32 x 2 hardware cursor

❑ Video Acceleration
• Video (YUV) and Graphics (RGB) shared frame buffer architecture
• Two-dimensional bilinear interpolation scaling with 1-pixel resolution from 1x to 8x
• On-chip standard CCIR 601 YUV to RGB color space conversion
• Cropping window and filtering supports
• Hardware support for Microsoft DirectDraw feature set
   □  Double buffering and page flipping to prevent from tearing in image
   □  Transparent BitBLTs of sprites for game acceleration
   □  Color keying, chroma keying and window keying to overlay video and Graphics streams
   □  On-the-fly blending of video and Graphics streams
• Supports 2x scaling to allow 320´200 game image to be displayed at 640 x 480 full-screen resolution
• High-quality video playback requiring only 1 MByte DRAM in 1024 x 768 256-color mode
• Dual hardware-accelerated video windows for video conference applications

❑ Multimedia Video Interface
• Glueless MPEG-1 video decoder (W9920DF) support for YUV 4:2:2 video input
• Glueless TV decoder support for YUV 4:2:2, NTSC or PAL live-video input
• Support for RGB 5:5:5, 5:6:5 or YUV 4:2:2 software CODEC video input
• Glueless support for 16-bit baseline VESA Advanced Feature Connector (VAFC)
• Glueless support for 8-bit bidirectional pass-through VGA feature connector

❑ Compatibility
• 100% hardware compatible with IBM VGA standard
• VESA BIOS extension support and VESA monitor timing compliant
• Driver support for all major operating systems, such as Windows 3.1, Windows 95, Windows NT, and OS/2 Warp 3.0
(Continue ...)

Description : 128 x 128-dot Graphics LCD Controller/Driver with Four-grayscale Functions

Description
The HD66750/1, dot-matrix Graphics LCD controller and driver LSI, displays 128-by-128-dot Graphics for four monochrome grayscales. Since the HD66750/1 incorporates bit-operation functions and a 16-bit high-speed bus interface, it enables efficient data transfer and high-speed rewriting of data in the Graphics RAM. The following functions allow the user to easily see a variety of information: a smooth scroll display function that fixed-displays a part of the Graphics icons and perform vertical smooth scrolling of the remaining bit-map areas, a double-height display function, and a hardware-supported window cursor display function.

Features
● 128 x 128-dot Graphics display LCD controller/driver for four monochrome grayscales
● Fixed display of Graphics icons (pictograms)
● 16-/8-bit high-speed bus interface capability
● Bit-operation functions for Graphics processing incorporated:
   - Write-data mask function in bit units
   - Bit rotation function
   - Bit logic-operation function
● Low-power operation support:
   - Vcc = 1.8 to 3.6 V (low voltage)
   - VLCD = 5 to 15.5 V (liquid crystal drive voltage)
   - Two-, five-, six-, or seven-times booster for liquid crystal drive voltage
   - 64-step contrast adjuster and voltage followers to decrease direct current flow in the LCD drive bleeder-resistors
   - Power-save functions such as the standby mode and sleep mode supported
   - Programmable drive duty ratios and bias values displayed on LCD
● 128-segment x 128-common liquid crystal display driver
● n-raster-row AC liquid-crystal drive (C-pattern waveform drive)
● Duty ratio and drive bias (selectable by program)
● Window cursor display supported by hardware
● Vertical smooth scroll
● Partial smooth scroll control (fixed display of Graphics icons)
● Vertical double-height display by each display raster-row
● Black-and-white reversed display
● No wait time for instruction execution and RAM access
● Internal oscillation and hardware reset
● Shift change of segment and common driver

Part Name(s) : S1D13700
EPSON
Seiko Epson Corp
Description : Embedded Memory Graphics LCD Controller

Overview Description
The S1D13700 Embedded Memory Graphics LCD Controller can display both text and Graphics on an LCD panel. The S1D13700 allows layered text and Graphics, scrolling of the display in any direction, and partitioning of the display into multiple screens. It includes 32K bytes of embedded SRAM display memory which is used to store text, character codes, and bit-mapped Graphics. The S1D13700 handles display controller functions including: transferring data from the controlling microprocessor to the buffer memory, reading memory data, converting data to display pixels, and generating timing signals for the LCD panel.

Features
Internal Memory
    • Embedded 32K bytes of SRAM display memory 
Host CPU Interface
    • Direct Address Bus support for:
        • Generic Bus (Z80 family) microprocessor interface
        • MC68K family microprocessor interface
    • Indirect Address Bus support for:
        • Generic Bus (Z80 family) microprocessor interface
        • MC68K family microprocessor interface
        • M6800 family microprocessor interface
    • 8-bit CPU data bus interface
Display Support
    • 4-bit monochrome LCD interface
    • Maximum resolutions supported: 640x240 at 1 bpp 320x240 at 2 bpp 240x160 at 4 bpp
    • 1/2-duty to 1/256-duty LCD drive
Display Modes
    • 1/2/4 bit-per-pixel color depth support
    • Text, Graphics and combined text/Graphics display modes
    • Three overlapping screens in Graphics mode
    • Programmable cursor control
    • Smooth horizontal scrolling of all or part of the display in monochrome mode
    • Smooth vertical scrolling of all or part of the display in all modes
Character Generation
    • 160, 5x7 pixel characters in embedded mask-programmed character generator ROM (CGROM)
    • Up to 64, 8x8 pixel characters in character generator RAM (CGRAM)
    • Up to 256, 8x16 pixel characters in embedded character generator RAM (when CGROM is not used)
Power
    • Software initiated power save mode
    • Low power consumption
    • CORE VDD 3.0 to 3.6 volts
    • IO VDD 3.0 to 5.5 volts
Clock Source
    • Two terminal crystal or Single Oscillator input Input Clock (maximum 60 MHz) FPSHIFT Clock (maximum 15 MHz)
Package
    • TQFP13 - 64-pin Pb-used package
    • TQFP13 - 64-pin Pb-free package (lead free)

Part Name(s) : CX25858
Conexant
Conexant Systems
Description : 8-Channel Audio/Video Decoder with Integrated PCIe Interface

High Quality Audio and Video Decoders for Surveillance Applications

The CX25858 8-Channel Audio/Video Decoder with Integrated PCIe Interface was designed for surveillance applications. The CX25858 contains eight high quality NTSC/PAL video decoders with 10-bit A/Ds and 5-line comb filtering, to generate the highest quality digital video output with the lowest possible noise. This creates not only the best image quality for viewing, but enables lower bitrates for compression devices using the output of the CX25858.

Distinguishing Features
• Eight High-Quality NTSC/PAL video decoders:
   - Anti-alias filters
   - 10-bit A/Ds
   - 5-line comb filtering
   - Independent scaling
• Eight Mono audio A/Ds
   - Variable sample rates
   - I2S outputs
• Flexible digital video output formats at 27, 54, and 108 MHz
   - Byte-interleaved
   - Line-interleaved
   - Frame-interleaved (requires external DDR2 memory)
PCIe 1.1 x1 interface
• Interface to Maxim CODECs for bridging of compressed data to PCIe
• Tiling and cascading functions (requires external DDR2 memory)
• Programmable Motion Detection
• 48 GPIO pins

IDT
Integrated Device Technology
Description : 6-Output Very Low-Power PCIe Gen 1-2-3-4 Clock Generator

Description
The 9FGV0631C is a member of IDTs SOC-Friendly 1.8V very low-power PCIe clock family. The device has 6 output enables for clock management, 2 different spread spectrum levels in addition to spread off, and 2 selectable SMBus addresses.

Features
• LP-HCSL outputs; save 12 resistors compared to standard PCIe devices
• 54mW typical power consumption; reduced thermal concerns
• Outputs can optionally be supplied from any voltage between 1.05V and 1.8V; maximum power savings
• OE# pins; support DIF power management
• Programmable slew rate for each output; allows tuning for various line lengths
• Programmable output amplitude; allows tuning for various application environments
• DIF outputs blocked until PLL is locked; clean system start-up
• Selectable 0%, -0.25% or -0.5% spread on DIF outputs; reduces EMI
• External 25MHz crystal; supports tight ppm with 0 ppm synthesis error
• Configuration can be accomplished with strapping pins; SMBus interface not required for device control
• 3.3V tolerant SMBus interface works with legacy controllers
• Selectable SMBus addresses; multiple devices can easily share an SMBus segment
• Space saving 5 x 5 mm 40-VFQFPN; minimal board space

Output Features
• 6 100MHz Low-Power (LP) HCSL DIF pairs
• 1 1.8V LVCMOS REF output w/Wake-On-LAN (WOL) support

Typical Applications
PCIe Gen1–4 clock generation for Riser Cards, Storage, Networking, JBOD, Communications, Access Points

Description : 6-Output Very Low-Power PCIe Gen 1-2-3-4 Clock Generator with Zo=100ohms

Description
The 9FGV0641 is a member of IDTs SOC-Friendly 1.8V very low-power PCIe clock family. The device has integrated 100Ω output terminations providing direction connection to 100Ω transmission lines. The device also has 6 output enables for clock management and supports 2 different spread spectrum levels in addition to spread off.

Features
• LP-HCSL outputs with integrated terminations; save 24 resistors compared to standard PCIe devices
• 54mW typical power consumption; reduced thermal concerns
• Outputs can optionally be supplied from any voltage between 1.05V and 1.8V; maximum power savings
• OE# pins; support DIF power management
• Programmable slew rate for each output; allows tuning for various line lengths
• Programmable output amplitude; allows tuning for various application environments
• DIF outputs blocked until PLL is locked; clean system start-up
• Selectable 0%, -0.25% or -0.5% spread on DIF outputs; reduces EMI
• External 25MHz crystal; supports tight ppm with 0 ppm synthesis error
• Configuration can be accomplished with strapping pins; SMBus interface not required for device control
• 3.3V tolerant SMBus interface works with legacy controllers
• Selectable SMBus addresses; multiple devices can easily share an SMBus segment
• Space saving 5 x 5 mm 40-VFQFPN; minimal board space

Output Features
• 6 100MHz Low-Power (LP) HCSL DIF pairs with Zo = 100Ω
• 1 1.8V LVCMOS REF output with Wake-On-LAN (WOL) support

Typical Applications
PCIe Gen1–4 clock generation for Riser Cards, Storage, Networking, JBOD, Communications, Access Points

IDT
Integrated Device Technology
Description : 8-Output Very Low-Power PCIe Gen 1-2-3-4 Clock Generator

Description
The 9FGV0831 is a member of IDTs SOC-friendly 1.8V very low-power PCIe clock family. The device has 8 output enables for clock management, 2 different spread spectrum levels in addition to spread off, and 2 selectable SMBus addresses.

Features/Benefits
• LP-HCSL outputs; saves 16 resistors compared to standard PCIe devices
• 62mW typical power consumption; reduced thermal concerns
• Outputs can optionally be supplied from any voltage between 1.05 and 1.8V; maximum power savings
• OE# pins; support DIF power management
• Programmable slew rate for each output; allows tuning for various line lengths
• Programmable output amplitude; allows tuning for various application environments
• DIF outputs blocked until PLL is locked; clean system start-up
• Selectable 0%, -0.25% or -0.5% spread on DIF outputs; reduces EMI
• External 25MHz crystal; supports tight ppm with 0 ppm synthesis error
• Configuration can be accomplished with strapping pins; SMBus interface not required for device control
• 3.3V tolerant SMBus interface works with legacy controllers
• Selectable SMBus addresses; multiple devices can easily share an SMBus segment
• Space saving 6 x 6 mm 48-VFQFPN; minimal board space

Output Features
• 8 100MHz Low-Power (LP) HCSL DIF pair
• 1 1.8V LVCMOS REF output with Wake-On-LAN (WOL) support

Recommended Application
PCIe Gen1–4 clock generation for Riser Cards, Storage, Networking, JBOD, Communications, Access Points

IDT
Integrated Device Technology
Description : 8-Output Very Low-Power PCIe Gen1-2-3-4 Clock Generator with Zo=100ohms

Description
The 9FGV0841 is a member of IDTs SOC-friendly 1.8V very low-power PCIe clock family. It has integrated output terminations providing Zo = 100Ω for direction connection to 100Ω transmission lines. The device has 8 output enables for clock management, 2 different spread spectrum levels in addition to spread off, and 2 selectable SMBus addresses.

Features
• Direct connection to 100Ω transmission lines; saves 32 resistors compared to standard PCIe devices
• 62mW typical power consumption; reduced thermal concerns
• Outputs can optionally be supplied from any voltage between 1.05 and 1.8V; maximum power savings
• OE# pins; support DIF power management
• LP-HCSL differential clock outputs; reduced power and board space
• Programmable slew rate for each output; allows tuning for various line lengths
• Programmable output amplitude; allows tuning for various application environments
• DIF outputs blocked until PLL is locked; clean system start-up
• Selectable 0%, -0.25% or -0.5% spread on DIF outputs; reduces EMI
• External 25MHz crystal; supports tight ppm with 0 ppm synthesis error
• Configuration can be accomplished with strapping pins; SMBus interface not required for device control
• 3.3V tolerant SMBus interface works with legacy controllers
• Selectable SMBus addresses; multiple devices can easily share an SMBus segment
• Space saving 6 x 6 mm 48-VFQFPN; minimal board space

Output Features
• 8 100MHz Low-Power (LP) HCSL DIF pairs with Zo = 100Ω
• 1 1.8V LVCMOS REF output with Wake-On-LAN (WOL) support

Typical Applications
PCIe Gen1–4 clock generation for Riser Cards, Storage, Networking, JBOD, Communications, Access Points

Description : EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIe GEN1,2,3

Description
The 9DB833 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB833 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator.

Features/Benefits
• 3 Selectable SMBus Addresses; mulitple devices can share the same SMBus Segment
• OE# pins; suitable for Express Card applications
• PLL or bypass mode; PLL can dejitter incoming clock
• Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs
• Spread Spectrum Compatible; tracks spreading input clock for low EMI
• SMBus Interface; unused outputs can be disabled
• Supports undriven differential outputs in Power Down mode for power management

Output Features
• 8 - 0.7V current-mode differential HCSL output pairs
• Supports zero delay buffer mode and fanout mode
• Selectable bandwidth
• 50-110 MHz operation in PLL mode
• 5-166 MHz operation in Bypass mode

Key Specifications
• Outputs cycle-cycle jitter <50ps
• Output to Output skew <50ps
• Phase jitter: PCIe Gen3 <1.0ps rm

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