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Philips
Philips Electronics
Description : 20-bit bus interface D-TYPE LATCH (3-STATE)

DESCRIPTION
The 74ALVCH16841 has two 10-bit D-TYPE LATCH featuring separate D-TYPE inputs for each LATCH and 3-STATE OUTPUTS for bus oriented applications. The two sections of each register are controlled independently by the LATCH enable (nLE) and output enable (nOE) control gates.

FEATURES
• Wide supply voltage range of 1.2V to 3.6V
• Complies WITH JEDEC standard no. 8-1A
• Wide supply voltage range of 1.2V to 3.6V
• CMOS low power consumption
• Direct interface WITH TTL levels
• MULTIBYTETM flow-through standard pin-out architecture
• Low inductance multiple VCC and GND pins for minimum noise and ground bounce
• Current drive ±24 mA at 3.0 V
• All inputs have bus hold circuitry
• Output drive capability 50Ω transmission lines @ 85°C
3-STATE non-inverting OUTPUTS for bus oriented applications

 

NXP
NXP Semiconductors.
Description : 18-bit BUS-INTERFACE D-TYPE LATCH; 3-STATE

General description
The 74ALVCH16843 has two 9–bit D-TYPE LATCH featuring separate D-TYPE inputs for each LATCH and 3-STATE OUTPUTS for bus oriented applications.
   
Features and benefits
• Wide supply voltage range of 1.2V to 3.6V
• CMOS low power consumption
• Direct interface WITH TTL levels
• Current drive ±24 mA at VCC = 3.0 V.
• MULTIBYTE flow-through standard pin-out architecture
• Low inductance multiple VCC and GND pins
    for minimize noise and ground bounce
• All data inputs have bushold
• Output drive capability 50 Ω transmission lines at 85 °C
3-STATE non-inverting OUTPUTS for bus oriented applications
• Complies WITH JEDEC standards:
    – JESD8-5 (2.3 V to 2.7 V)
    – JESD8B/JESD36 (2.7 V to 3.6 V)
• ESD protection:
    – HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V
    – CDM JESD22-C101E exceeds 1000 V
   

Philips
Philips Electronics
Description : 18-bit BUS-INTERFACE D-TYPE LATCH (3-STATE)

DESCRIPTION
The 74ALVCH16843 has two 9–bit D-TYPE LATCH featuring separate D-TYPE inputs for each LATCH and 3-STATE OUTPUTS for bus oriented applications.
   
FEATURES
• Wide supply voltage range of 1.2V to 3.6V
• Complies WITH JEDEC standard no. 8-1A.
• CMOS low power consumption
• Direct interface WITH TTL levels
• Current drive ± 24 mA at 3.0 V
• MULTIBYTETM flow-through standard pin-out architecture
• Low inductance multiple VCC and GND pins for minimum noise
    and ground bounce
• All data inputs have bus hold
• Output drive capability 50Ω transmission lines @ 85°C
   

ST-Microelectronics
STMicroelectronics
Description : 16-BIT D-TYPE LATCH PULS 16-BIT BUS BUFFER WITH 3-STATE OUTPUTS (NON INVERTED)

DESCRIPTION
The 74ACT16244 is a low voltage CMOS 16-BIT D-TYPE LATCH and 16 BIT BUS TRANSCEIVER WITH 3-STATE output non inverting fabricated WITH sub-micron silicon gate and double-layer metal wiring C2MOS technology.
Both functions can be used as 16 bit or dual octal devices, so the 16 bit transceiver can be used ad 8 bit bus buffer plus 8 bit transceiver, or only 16 bit buffer in select direction.

■ HIGH SPEED: tPD = 4.8ns (TYP.) at VCC = 5V
■ LOW POWER DISSIPATION: ICC = 8µA(MAX.) at TA=25°C
■ COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.), VIL = 0.8V (MAX.)
■ SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 4.5V
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V
■ FUNCTION COMPATIBLE WITH SERIES 16373 AND 16245 (244)
■ IMPROVED LATCH-UP IMMUNITY
■ IMPROVED ESD IMMUNITY

Pericom-Semiconductor
Pericom Semiconductor
Description : 20-Bit BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS

Product Description
Pericom Semiconductor’s PI74ALVCH series of logic circuits are produced in the Company’s advanced 0.5 micron CMOS technology, achieving industry leading speed.

Product Features
• PI74ALVCH16841 is designed for low voltage operation
• VCC = 2.3V to 3.6V
• Hysteresis on all inputs
• Typical VOLP (Output Ground Bounce)
    < 0.8V at VCC = 3.3V, TA = 25°C
• Typical VOHV (Output VOH Undershoot)
    < 2.0V at VCC = 3.3V, TA = 25°C
• Bus Hold retains last active bus state during 3-STATE, eliminating the need for external pullup resistors
• Industrial operation at –40°C to +85°C
• Packages available:
    - 56-pin 240 mil wide plastic TSSOP (A)
    - 56-pin 300 mil wide plastic SSOP (V)

Description : 3.3V CMOS 16-BIT TRANS-PARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND BUS-HOLD

DESCRIPTION:
This 16-bit transparent D-TYPE LATCH is built using advanced dual metal CMOS technology. The ALVCH162373 is particularly suitable for imple-menting buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit LATCHes or one16-bit LATCH. When the LATCH enable (LE) input is high, the Q OUTPUTS follow the data (D) inputs. When LE is taken low, the Q OUTPUTS are LATCHed at the levels set up at the D inputs.

FEATURES:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP and TSSOP packages

DRIVE FEATURES:
• Balanced Output Drivers: ±12mA
• Low switching noise

APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems

Part Name(s) : MB2841BB MB2841
Philips
Philips Electronics
Description : Dual 10-bit bus interface LATCH (3-STATE)

DESCRIPTION
The MB2841 Bus interface register is designed to provide extra data width for wider data/address paths of buses carrying parity.
The MB2841 consists of two sets of ten D-TYPE LATCHes WITH 3-STATE OUTPUTS. The flip-flops appear transparent to the data when LATCH Enable (nLE) is High. This allows asynchronous operation, as the output transition follows the data in transition. On the nLE High-to-Low transition, the data that meets the setup and hold time is LATCHed.
Data appears on the bus when the Output Enable (nOE) is Low. When nOE is High the output is in the High-impedance state.

FEATURES
• High speed parallel LATCHes
• Live insertion/extraction permitted
• Extra data width for wide address/data
   paths or buses carrying parity
• Power-up 3-STATE
• Power-up reset
• Ideal where high speed, light loading, or
   increased fan-in are required WITH MOS microprocessors
• Output capability: +64mA/–32mA
LATCH-up protection exceeds 500mA per Jedec JC40.2 Std 17
• ESD protection exceeds 2000V per MIL
   STD 883 Method 3015 and 200V per Machine Model

Description : 16-bit D-TYPE transparent LATCH WITH 5 V tolerant inputs/OUTPUTS; 3-STATE

DESCRIPTION
The 74LVC(H)16373A is a 16-bit D-TYPE transparent LATCH featuring separate D-TYPE inputs for each LATCH and 3-STATE OUTPUTS for bus oriented applications. One LATCH Enable (LE) input and one Output Enable (OE) are provided for each octal. Inputs can be driven from either 3.3 or 5 V devices. In 3-STATE operation, OUTPUTS can handle 5 V. These features allow the use of these devices in a mixed 3.3 and 5 V environment.

FEATURES
• 5 V tolerant inputs/OUTPUTS for interfacing WITH 5 V logic
• Wide supply voltage range from 1.2 to 3.6 V
• CMOS low power consumption
• MULTIBYTE flow-through standard pin-out architecture
• Low inductance multiple power and ground pins for minimum noise and ground bounce
• Direct interface WITH TTL levels
• All data inputs have bushold (74LVCH16373A only)
• High-impedance when VCC = 0 V.
• Complies WITH JEDEC standard no. 8-1A
• ESD protection:
  HBM EIA/JESD22-A114-A exceeds 2000 V
  MM EIA/JESD22-A115-A exceeds 200 V.
• Specified from −40 to +85 °C and −40 to +125 °C.

Description : 16-bit D-TYPE transparent LATCH; 30Ω series termination resistors; 5 V tolerant inputs/OUTPUTS; 3-STATE

General description
The 74LVC162373A and 74LVCH162373A are 16-bit D-TYPE transparent LATCHes WITH separate D-TYPE inputs WITH bus hold (74LVCH162373A only) for each LATCH and 3-STATE OUTPUTS for bus-oriented applications.
   
Features and benefits
■ 5 V tolerant inputs/OUTPUTS for interfacing WITH 5 V logic
■ Wide supply voltage range from 1.2 V to 3.6 V
■ CMOS low power consumption
■ Multibyte flow-through standard pinout architecture
■ Multiple low inductance supply pins for minimum noise and ground bounce
■ Direct interface WITH TTL levels
■ All data inputs have bus hold (74LVCH162373A only)
■ High-impedance when VCC = 0 V
■ Complies WITH JEDEC standard:
    ◆ JESD8-7A (1.65 V to 1.95 V)
    ◆ JESD8-5A (2.3 V to 2.7 V)
    ◆ JESD8-C/JESD36 (2.7 V to 3.6 V)
       

Description : 3.3V LVT 16-bit transparent D-TYPE LATCH (3-STATE)

DESCRIPTION
The 74LVT16373A is a high-performance BiCMOS product designed for VCC operation at 3.3V.
This device is a 16-bit transparent D-TYPE LATCH WITH non-inverting 3-STATE bus compatible OUTPUTS. The device can be used as two 8-bit LATCHes or one 16-bit LATCH. When enable (E) input is High, the Q OUTPUTS follow the data (D) inputs. When enable is taken Low, the Q OUTPUTS are LATCHed at the levels of the D inputs one setup time prior to the High-to-Low transition.

FEATURES
• 16-bit transparent LATCH
3-STATE buffers
• Output capability: +64mA/-32mA
• TTL input and output switching levels
• Input and output interface capability to systems at 5V supply
• Bus-hold data inputs eliminate the need for external pull-up
   resistors to hold unused inputs
• Live insertion/extraction permitted
• Power-up reset
• Power-up 3-STATE
• No bus current loading when output is tied to 5V bus
LATCH-up protection exceeds 500mA per JEDEC Std 17
• ESD protection exceeds 2000V per MIL STD 883 Method 3015
   and 200V per Machine Model

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