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Part Name(s) : W25P222A W25P222A-4 W25P222A-4A W25P222AF-4 W25P222AF-4A W25P222AD-4 W25P222AD-4A Winbond
Winbond
Description : 64K X 32 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM View

64K X 32 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM

Part Name(s) : W25P240A-6A W25P240AF-6 W25P240AF-6A W25P240A Winbond
Winbond
Description : 64K x 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM View

GENERAL DESCRIPTION
The W25P240A is a HIGH-SPEED, low-power, synchronous-BURST PIPELINED CMOS STATIC RAM organized as 65,536 x 64 bits that operates on a single 3.3-volt power supply. A built-in two-bit BURST address counter supports Pentiumä BURST mode.

FEATURES
• Synchronous operation
• Support 66/75 MHz bus speed
• Single +3.3V power supply
• Individual byte write capability
• 3.3V LVTTL compatible I/O
• Clock-controlled and registered input
• Asynchronous output enable
• Internal BURST counter supports Intel BURST mode
• Packaged in 100-pin QFP

Part Name(s) : W25P243A W25P243A-4A W25P243A-5 W25P243A-6 W25P243AD-4A W25P243AD-5 W25P243AD-6 W25P243AF-4A W25P243AF-5 W25P243AF-6 Winbond
Winbond
Description : 64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM View

GENERAL DESCRIPTION
The W25P243A is a HIGH-SPEED, low-power, synchronous-BURST PIPELINED, CMOS STATIC RAM organized as 65,536 X 64 bits that operates on a single 3.3-volt power supply. A built-in two-bit BURST address counter supports both Pentiumä BURST mode and linear BURST mode. The mode to be executed is controlled by the LBO pin. Pipelining or non-pipelining of the data outputs is controlled by the FT pin. A snooze mode can reduce power dissipation.

FEATURES
• Synchronous operation
HIGH-SPEED access time: 4.5/5/6 nS (max.)
• Single +3.3V power supply
• Individual byte write capability
• 3.3V LVTTL compatible I/O
• Clock-controlled and registered input
• Asynchronous output enable
PIPELINED data output capability
• Supports snooze mode (low-power state)
• Internal BURST counter supports Intel BURST (Interleaved) mode & linear BURST mode
• Support 2T/1T mode
• Packaged in 128-pin QFP and TQFP

 

Part Name(s) : IDT61298SA IDT61298SA12Y IDT61298SA15Y IDT
Integrated Device Technology
Description : CMOS STATIC RAM 256K (64K x 4-BIT) View

DESCRIPTION:
The lDT61298SA is a 262,144-bit HIGH-SPEED STATIC RAM organized as 64K x 4. It is fabricated using IDT’s high-performance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design echniques, provides a cost-effective approach for memory ntensive applications.

FEATURES:
64K x 4 HIGH-SPEED STATIC RAM
• Fast Output Enable (OE) pin available for added system flexibility
• High speed (equal access and cycle times)
    — Commercial: 12/15 ns (max.)
• JEDEC standard pinout
• 300 mil 28-pin SOJ
• Produced with advanced CMOS technology
• Bidirectional data inputs and outputs
• Inputs/Outputs TTL-compatible
• Three-state outputs
• Military product compliant to MIL-STD-883, Class B


Part Name(s) : MCM69T618 MCM69T618TQ5 MCM69T618TQ5R Motorola
Motorola => Freescale
Description : 64K x 18 Bit Synchronous PIPELINED Cache Tag RAM View

The MCM69T618 is a 1M–bit synchronous fast STATIC RAM with integrated tag compare function. It is designed to address tag RAM for 512KB, 1MB, or 2MB secondary cache as well as to be used as a data RAM for 512KB caches. This device is organized as 64K words of 18 bits each. It integrates input registers, output registers, tag comparators, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache tag RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.
   
• MCM69T618–5 = 5 ns Clock–to–Match / 10 ns cycle
• Single 3.3 V + 10%, – 5% Power Supply
PIPELINED Data Comparator
PIPELINED Chip Enable and Write Enable for Data (DQ) Output Enable Path
64K x 18 Organization Supports Up to 2MB Cache
• Synchronous Data Input Register Load Enable (DE)
• Internally Self–Timed Write Cycle
• Asynchronous Data I/O Output Enable (G)
• Asynchronous Match Output Enable (MG)
• 100–Pin TQFP Package
   

Part Name(s) : IS61LP6432A IS61LP6432A-133TQ IS61LP6432A-133TQI IS61LP6432A-133TQLI IS61LP6436A IS61LP6436A-133TQ IS61LP6436A-166TQ IS61LP6436A-166TQI IS61LP6436A-166TQLI IS61LP6436A-133TQI IS61LP6436A-133TQLI ISSI
Integrated Silicon Solution
Description : 64K x 32, 64K x 36 SYNCHRONOUS PIPELINED STATIC RAM View

DESCRIPTION
The ISSI IS61LP6432A/36A is a HIGH-SPEED synchronous STATIC RAM designed to provide a BURSTable, high-performance memory for high speed networking and communication applications. The IS61LP6432A is organized as 64K words by 32 bits and the IS61LP6436A is organized as 64K words by 36 bits. Fabricated with ISSIs advanced CMOS technology, the device integrates a 2-bit BURST counter, highspeed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input.

FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and control
• Pentium™ or linear BURST sequence control using MODE input
• Three chip enables for simple depth expansion and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP package
• Power-down snooze mode
• Power Supply:
    +3.3V VDD
    +3.3V or 2.5V VDDQ (I/O)
• Lead-free available

Part Name(s) : MCM63P631 MCM63P631TQ117 MCM63P631TQ117R MCM63P631TQ4.5 MCM63P631TQ4.5R MCM63P631TQ7 MCM63P631TQ7R MCM63P631TQ8 MCM63P631TQ8R MCM63P631-117 MCM63P631-4.5 MCM63P631-7 MCM63P631-8 Motorola
Motorola => Freescale
Description : 64K x 32 Bit PIPELINED BURSTRAM Synchronous Fast STATIC RAM View

The MCM63P631 is a 2M bit synchronous fast STATIC RAM designed to provide a BURSTable, high performance, secondary cache for the 68K Family, PowerPC, and Pentium microprocessors. It is organized as 64K words of 32 bits each. This device integrates input registers, an output register, a 2–bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.

• MCM63P631–117 = 4.5 ns access / 8.5 ns cycle (117 MHz)
    MCM63P631–4.5 = 4.5 ns access / 10 ns cycle (100 MHz)
    MCM63P631–7 = 7 ns access / 13.3 ns cycle (75 MHz)
    MCM63P631–8 = 8 ns access / 15 ns cycle (66 MHz)
• Single 3.3 V + 10%, – 5% Power Supply
• ADSP, ADSC, and ADV BURST Control Pins
• Selectable BURST Sequencing Order (Linear/Interleaved)
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• Sleep Mode (ZZ)
• PB1 Version 2.0 Compatible
• Single–Cycle Deselect Timing
• JEDEC Standard 100–Pin TQFP Package

Part Name(s) : EDI9F37512C EDI9F37512C45MMC EDI9F37512C55MMC ETC
Unspecified
Description : 512Kx37 STATIC RAM CMOS, High Speed Module View

[WEDC]

DESCRIPTION
The EDI9F37512C is a high speed 20 megabit STATIC RAM module organized as 512K words x 37 bits. This module is constructed from five 512Kx8 STATIC RAMs in TSOP packages on an epoxy laminate (FR4) board.

FEATURES
• 512Kx37 bit CMOS STATIC RAM
    • Access Times: 45 and 55ns
    • Individual Byte Selects
    • Fully STATIC, No Clocks
    • TTL Compatible I/O
• High Density Package
    • 72 lead SIMM, No. 418
    • Common Data Inputs and Outputs
• Single +5V (–10%) Supply Operation

Part Name(s) : IS61LV6424 IS61LV6424-10TQ IS61LV6424-10TQI IS61LV6424-12TQ IS61LV6424-12TQI IS61LV6424-15TQ IS61LV6424-15TQI IS61LV6424-9TQ IS61LV6424-9TQI ISSI
Integrated Silicon Solution
Description : 64K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY View

DESCRIPTION
The ICSIIS61LV6424 is a HIGH-SPEED, STATIC RAM organized as 65,536 words by 24 bits. It is fabricated using ICSI's high performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 9 ns with low power consumption.

FEATURES
HIGH-SPEED access time: 9, 10, 12, 15 ns
CMOS low power operation
—594 mW (max.) operating @ 9 ns
—36 mW (max.) CMOS standby
• TTL compatible interface levels
• Single 3.3V power supply
• Fully STATIC operation: no clock or refresh required
• Three state outputs
• Available in 100-pin LQFP

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