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Part Name(s) : W25P222A W25P222A-4 W25P222A-4A W25P222AF-4 W25P222AF-4A W25P222AD-4 W25P222AD-4A Winbond
Winbond
Description : 64K X 32 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM View

64K X 32 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM

Part Name(s) : W25P240A-6A W25P240AF-6 W25P240AF-6A W25P240A Winbond
Winbond
Description : 64K x 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM View

GENERAL DESCRIPTION
The W25P240A is a HIGH-SPEED, low-power, synchronous-BURST PIPELINED CMOS STATIC RAM organized as 65,536 x 64 bits that operates on a single 3.3-volt power supply. A built-in two-bit BURST address counter supports Pentiumä BURST mode.

FEATURES
• Synchronous operation
• Support 66/75 MHz bus speed
• Single +3.3V power supply
• Individual byte write capability
• 3.3V LVTTL compatible I/O
• Clock-controlled and registered input
• Asynchronous output enable
• Internal BURST counter supports Intel BURST mode
• Packaged in 100-pin QFP

Part Name(s) : W25P243A W25P243A-4A W25P243A-5 W25P243A-6 W25P243AD-4A W25P243AD-5 W25P243AD-6 W25P243AF-4A W25P243AF-5 W25P243AF-6 Winbond
Winbond
Description : 64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM View

GENERAL DESCRIPTION
The W25P243A is a HIGH-SPEED, low-power, synchronous-BURST PIPELINED, CMOS STATIC RAM organized as 65,536 X 64 bits that operates on a single 3.3-volt power supply. A built-in two-bit BURST address counter supports both Pentiumä BURST mode and linear BURST mode. The mode to be executed is controlled by the LBO pin. Pipelining or non-pipelining of the data outputs is controlled by the FT pin. A snooze mode can reduce power dissipation.

FEATURES
• Synchronous operation
HIGH-SPEED access time: 4.5/5/6 nS (max.)
• Single +3.3V power supply
• Individual byte write capability
• 3.3V LVTTL compatible I/O
• Clock-controlled and registered input
• Asynchronous output enable
PIPELINED data output capability
• Supports snooze mode (low-power state)
• Internal BURST counter supports Intel BURST (Interleaved) mode & linear BURST mode
• Support 2T/1T mode
• Packaged in 128-pin QFP and TQFP

 

Part Name(s) : MCM63P631A MCM63P631ATQ117 MCM63P631ATQ100 MCM63P631ATQ117R MCM63P631ATQ100R MCM63P631ATQ75 MCM63P631ATQ66 MCM63P631ATQ75R MCM63P631ATQ66R Motorola
Motorola => Freescale
Description : 64K x 32 Bit PIPELINED BURSTRAM Synchronous Fast STATIC RAM View

The MCM63P631A is a 2M bit synchronous fast STATIC RAM designed to provide a BURSTable, high performance, secondary cache for the 68K Family, PowerPC, and Pentium microprocessors. It is organized as 64K words of 32 bits each. This device integrates input registers, an output register, a 2–bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.
The MCM63P631A operates from a 3.3 V power supply, all inputs and outputs are LVTTL compatible.

• MCM63P631A–117 = 4.5 ns access / 8.5 ns cycle (117 MHz)
    MCM63P631A–100 = 4.5 ns access / 10 ns cycle (100 MHz)
    MCM63P631A–75 = 7 ns access / 13.3 ns cycle (75 MHz)
    MCM63P631A–66 = 8 ns access / 15 ns cycle (66 MHz)
• Single 3.3 V + 10%, – 5% Power Supply
• ADSP, ADSC, and ADV BURST Control Pins
• Selectable BURST Sequencing Order (Linear/Interleaved)
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• Sleep Mode (ZZ)
• PB1 Version 2.0 Compatible
• Single–Cycle Deselect Timing
• JEDEC Standard 100–Pin TQFP Package


Part Name(s) : MCM63P631 MCM63P631TQ117 MCM63P631TQ117R MCM63P631TQ4.5 MCM63P631TQ4.5R MCM63P631TQ7 MCM63P631TQ7R MCM63P631TQ8 MCM63P631TQ8R MCM63P631-117 MCM63P631-4.5 MCM63P631-7 MCM63P631-8 Motorola
Motorola => Freescale
Description : 64K x 32 Bit PIPELINED BURSTRAM Synchronous Fast STATIC RAM View

The MCM63P631 is a 2M bit synchronous fast STATIC RAM designed to provide a BURSTable, high performance, secondary cache for the 68K Family, PowerPC, and Pentium microprocessors. It is organized as 64K words of 32 bits each. This device integrates input registers, an output register, a 2–bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.

• MCM63P631–117 = 4.5 ns access / 8.5 ns cycle (117 MHz)
    MCM63P631–4.5 = 4.5 ns access / 10 ns cycle (100 MHz)
    MCM63P631–7 = 7 ns access / 13.3 ns cycle (75 MHz)
    MCM63P631–8 = 8 ns access / 15 ns cycle (66 MHz)
• Single 3.3 V + 10%, – 5% Power Supply
• ADSP, ADSC, and ADV BURST Control Pins
• Selectable BURST Sequencing Order (Linear/Interleaved)
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• Sleep Mode (ZZ)
• PB1 Version 2.0 Compatible
• Single–Cycle Deselect Timing
• JEDEC Standard 100–Pin TQFP Package

Part Name(s) : IDT61298SA IDT61298SA12Y IDT61298SA15Y IDT
Integrated Device Technology
Description : CMOS STATIC RAM 256K (64K x 4-BIT) View

DESCRIPTION:
The lDT61298SA is a 262,144-bit HIGH-SPEED STATIC RAM organized as 64K x 4. It is fabricated using IDT’s high-performance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design echniques, provides a cost-effective approach for memory ntensive applications.

FEATURES:
64K x 4 HIGH-SPEED STATIC RAM
• Fast Output Enable (OE) pin available for added system flexibility
• High speed (equal access and cycle times)
    — Commercial: 12/15 ns (max.)
• JEDEC standard pinout
• 300 mil 28-pin SOJ
• Produced with advanced CMOS technology
• Bidirectional data inputs and outputs
• Inputs/Outputs TTL-compatible
• Three-state outputs
• Military product compliant to MIL-STD-883, Class B

Part Name(s) : A63G7332 A63G7332E-4.2 A63G7332E-4.5 A63G7332E-42 A63G7332E-5 A63G7332E-45 AMICC
AMIC Technology
Description : 128K X 32 Bit Synchronous High Speed SRAM with BURST Counter and PIPELINED Data Output View

General Description
The A63G7332 is a HIGH-SPEED, low-power SRAM containing 4,194,304 bits of bit synchronous memory, organized as 131,072 words by 32 bits.
The A63G7332 combines advanced synchronous peripheral circuitry, 2-bit BURST control, input registers, output registers and a 128K X 32 SRAM core to provide a wide range of data RAM applications.

Features
■ Fast access times: 4.2/4.5/5.0 ns (143/133/100 MHZ)
■ Single +3.3V+10% or +3.3V-5% power supply
■ Separate +2.5V+0.4V/-0.12V isolated output buffer
■ 3.3V tolerant inputs
■ Synchronous BURST function
■ Individual Byte Write control and Global Write
■ Registered output for PIPELINED applications
■ Three separate chip enables allow wide range of options for CE control, address pipelining
■ Selectable BURST mode
■ SLEEP mode (ZZ pin) provided
■ Available in 100-pin LQFP package

Part Name(s) : CY7C1329_04 CY7C1329-133AC_04 CY7C1329-100AC_04 CY7C1329-100AI Cypress
Cypress Semiconductor
Description : 64K x 32 Synchronous-PIPELINED Cache RAM View

Features
• Supports 133-MHz bus for Pentium® and PowerPC
   operations with zero wait states
• Fully registered inputs and outputs for PIPELINED operation
64K x 32 common I/O architecture
• Single 3.3V power supply
• Fast clock-to-output times
   — 4.2 ns (for 133-MHz device)
   — 5.5 ns (for 100-MHz device)
• User-selectable BURST counter supporting Intel®
   Pentium interleaved or linear BURST sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• JEDEC-standard 100-lead TQFP pinout
• “ZZ” Sleep Mode option and Stop Clock option

Part Name(s) : CY7C1329 CY7C1329-133AC CY7C1329-100AC CY7C1329-75AC Cypress
Cypress Semiconductor
Description : 64K x 32 Synchronous-PIPELINED Cache RAM View

Features
• Supports 133-MHz bus for Pentium® and PowerPC™
   operations with zero wait states
• Fully registered inputs and outputs for PIPELINED operation
64K x 32 common I/O architecture
• Single 3.3V power supply
• Fast clock-to-output times
   — 4.2 ns (for 133-MHz device)
   — 5.5 ns (for 100-MHz device)
   — 7.0 ns (for 75-MHz device
• User-selectable BURST counter supporting Intel®
   Pentium interleaved or linear BURST sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• JEDEC-standard 100 TQFP pinout
• “ZZ” Sleep Mode option and Stop Clock option

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