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Description : 64K X 32 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM

64K X 32 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM

Description : 64K x 32 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM

GENERAL DESCRIPTION
The W25P022A is a HIGH-SPEED, low-power, synchronous-BURST PIPELINED CMOS STATIC RAM organized as 65,536 ´ 32 bits that operates on a single 3.3-volt power supply. A built-in two-bit BURST address counter supports both Pentiumä BURST mode and linear BURST mode. The mode to be executed is controlled by the LBO pin. Pipelining or non-pipelining of the data outputs is controlled by the FT pin. A snooze mode reduces power dissipation.

FEATURES
• Synchronous operation
HIGH-SPEED access time: 6/7 nS (max.)
• Single +3.3V power supply
• Individual byte write capability
• 3.3V LVTTL compatible I/O
• Clock-controlled and registered input
• Asynchronous output enable
PIPELINED/non-PIPELINED data output capability
• Supports snooze mode (low-power state)
• Internal BURST counter supports Intel BURST mode & linear BURST mode
• Supports both 2T/2T & 2T/1T mode
• Packaged in 100-pin QFP or TQFP

Description : 64K x 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM

GENERAL DESCRIPTION
The W25P240A is a HIGH-SPEED, low-power, synchronous-BURST PIPELINED CMOS STATIC RAM organized as 65,536 x 64 bits that operates on a single 3.3-volt power supply. A built-in two-bit BURST address counter supports Pentiumä BURST mode.

FEATURES
• Synchronous operation
• Support 66/75 MHz bus speed
• Single +3.3V power supply
• Individual byte write capability
• 3.3V LVTTL compatible I/O
• Clock-controlled and registered input
• Asynchronous output enable
• Internal BURST counter supports Intel BURST mode
• Packaged in 100-pin QFP

Description : 64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM

GENERAL DESCRIPTION
The W25P243A is a HIGH-SPEED, low-power, synchronous-BURST PIPELINED, CMOS STATIC RAM organized as 65,536 X 64 bits that operates on a single 3.3-volt power supply. A built-in two-bit BURST address counter supports both Pentiumä BURST mode and linear BURST mode. The mode to be executed is controlled by the LBO pin. Pipelining or non-pipelining of the data outputs is controlled by the FT pin. A snooze mode can reduce power dissipation.

FEATURES
• Synchronous operation
HIGH-SPEED access time: 4.5/5/6 nS (max.)
• Single +3.3V power supply
• Individual byte write capability
• 3.3V LVTTL compatible I/O
• Clock-controlled and registered input
• Asynchronous output enable
PIPELINED data output capability
• Supports snooze mode (low-power state)
• Internal BURST counter supports Intel BURST (Interleaved) mode & linear BURST mode
• Support 2T/1T mode
• Packaged in 128-pin QFP and TQFP

 

Description : 64K x 32 Bit PIPELINED BURSTRAM Synchronous Fast STATIC RAM

The MCM63P631A is a 2M bit synchronous fast STATIC RAM designed to provide a BURSTable, high performance, secondary cache for the 68K Family, PowerPC, and Pentium microprocessors. It is organized as 64K words of 32 bits each. This device integrates input registers, an output register, a 2–bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.
The MCM63P631A operates from a 3.3 V power supply, all inputs and outputs are LVTTL compatible.

• MCM63P631A–117 = 4.5 ns access / 8.5 ns cycle (117 MHz)
    MCM63P631A–100 = 4.5 ns access / 10 ns cycle (100 MHz)
    MCM63P631A–75 = 7 ns access / 13.3 ns cycle (75 MHz)
    MCM63P631A–66 = 8 ns access / 15 ns cycle (66 MHz)
• Single 3.3 V + 10%, – 5% Power Supply
• ADSP, ADSC, and ADV BURST Control Pins
• Selectable BURST Sequencing Order (Linear/Interleaved)
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• Sleep Mode (ZZ)
• PB1 Version 2.0 Compatible
• Single–Cycle Deselect Timing
• JEDEC Standard 100–Pin TQFP Package

Description : 64K x 32, 64K x 36 SYNCHRONOUS PIPELINED STATIC RAM

DESCRIPTION
The ISSI IS61LP6432A/36A is a HIGH-SPEED synchronous STATIC RAM designed to provide a BURSTable, high-performance memory for high speed networking and communication applications. The IS61LP6432A is organized as 64K words by 32 bits and the IS61LP6436A is organized as 64K words by 36 bits. Fabricated with ISSIs advanced CMOS technology, the device integrates a 2-bit BURST counter, highspeed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input.

FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and control
• Pentium™ or linear BURST sequence control using MODE input
• Three chip enables for simple depth expansion and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP package
• Power-down snooze mode
• Power Supply:
    +3.3V VDD
    +3.3V or 2.5V VDDQ (I/O)
• Lead-free available

Description : 64K x 36 Bit PIPELINED BURSTRAM Synchronous Fast STATIC RAM

64K x 36 Bit PIPELINED BURSTRAM Synchronous Fast STATIC RAM

The MCM63P636 is a 2M–bit synchronous fast STATIC RAM designed to provide BURSTable, high performance, secondary cache for advanced microprocessors. It is organized as 64K words of 36 bits each. This device integrates input registers, an output register, a 2–bit address counter, and a high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows for precise cycle control with the use of an external clock (K) and external strobe clock (SK).
The MCM63P636 operates from a 3.3 V core power supply, a 2.0 V input power supply, and a 2.0 V I/O power supply. These power supplies are designed so that power sequencing is not required.

• MCM63P636–250 = 3.9 ns Access/4 ns Cycle (250 MHz)
  MCM63P636–225 = 4.3 ns Access/4.4 ns Cycle (225 MHz)
  MCM63P636–200 = 4.9 ns Access/5 ns Cycle (200 MHz)
• 3.3 V ± 200 mV VDD Supply, 2.0 V VDDI and VDDQ Supply
• Internally Self–Timed Late Write Cycle
• Three–Cycle Single–Read Latency
• Strobe Clock Input and Data Strobe Output Pins
• On–Chip Output Enable Control
• On–Chip BURST Advance Control
• Four–Tick BURST
• Power–On Reset Pin
• Low Power Stop Clock Operation
• Boundary Scan (PBGA Only)
• JEDEC Standard 153–Pin PBGA and 100–Pin TQFP Packages

Description : 64K x 32 CMOS STATIC RAM Module

Description:
The PDM4M4030 is a 64K x 32 STATIC RAM module constructed on an epoxy laminate (FR-4) substrate using eight 64K x 4 STATIC RAMs in plastic SOJ packages. Availability of four chip select lines (one for each of two RAMs) provides byte access. Extremely fast speeds can be achieved due to the use of 256K STATIC RAMs fabricated in Paradigm’s high-performance, high-reliability CMOS technology. The PDM4M4030 is available with access times as fast as 10 ns with minimal power consumption.

Features:
□ High-density 2 megabit STATIC RAM module
□ Low profile 64-pin ZIP (Zig-zag In-line vertical Package), 64-pin SIMM or Angled SIMM (Single In-line Memory Module)
□ Ultra fast access time: 10 ns (max.)
□ Surface mounted plastic components on an epoxy laminate (FR-4) substrate
□ Single 5V (±10%) power supply
□ Multiple VSS pins and decoupling capacitors for maximum noise immunity
□ Inputs/outputs directly TTL compatible

Description : 64K x 32 Bit PIPELINED BURSTRAM Synchronous Fast STATIC RAM

The MCM63P631 is a 2M bit synchronous fast STATIC RAM designed to provide a BURSTable, high performance, secondary cache for the 68K Family, PowerPC, and Pentium microprocessors. It is organized as 64K words of 32 bits each. This device integrates input registers, an output register, a 2–bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.

• MCM63P631–117 = 4.5 ns access / 8.5 ns cycle (117 MHz)
    MCM63P631–4.5 = 4.5 ns access / 10 ns cycle (100 MHz)
    MCM63P631–7 = 7 ns access / 13.3 ns cycle (75 MHz)
    MCM63P631–8 = 8 ns access / 15 ns cycle (66 MHz)
• Single 3.3 V + 10%, – 5% Power Supply
• ADSP, ADSC, and ADV BURST Control Pins
• Selectable BURST Sequencing Order (Linear/Interleaved)
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• Sleep Mode (ZZ)
• PB1 Version 2.0 Compatible
• Single–Cycle Deselect Timing
• JEDEC Standard 100–Pin TQFP Package

IDT
Integrated Device Technology
Description : CMOS STATIC RAM 256K (64K x 4-BIT)

DESCRIPTION:
The lDT61298SA is a 262,144-bit HIGH-SPEED STATIC RAM organized as 64K x 4. It is fabricated using IDT’s high-performance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design echniques, provides a cost-effective approach for memory ntensive applications.

FEATURES:
64K x 4 HIGH-SPEED STATIC RAM
• Fast Output Enable (OE) pin available for added system flexibility
• High speed (equal access and cycle times)
    — Commercial: 12/15 ns (max.)
• JEDEC standard pinout
• 300 mil 28-pin SOJ
• Produced with advanced CMOS technology
• Bidirectional data inputs and outputs
• Inputs/Outputs TTL-compatible
• Three-state outputs
• Military product compliant to MIL-STD-883, Class B

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