datasheetbank_Logo     Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

P/N + Description + Content Search

Search Words :

Part Name(s) : HB52E649E12 HB52E649E12-A6B HB52E649E12-B6B Elpida
Elpida Memory, Inc
Description : 512 MB REGISTERED SDRAM DIMM 64-MWORD 72-BIT, 100 MHZ MEMORY BUS, 1-Bank Module (18 pcs of 64 M 4 Components) PC100 SDRAM View

Description
The HB52E649E12 belongs to 8-byte DIMM (Dual In-line MEMORY Module) family, and has been developed as an optimized main MEMORY solution for 8-byte processor applications. The HB52E649E12 is a 64M × 72 × 1-bank Synchronous Dynamic RAM REGISTERED Module, mounted 18 pieces of 256-MBit SDRAM (HM5225405BTT) sealed in TSOP package, 1 piece of PLL clock driver, 2 pieces of register driver and 1 piece of serial EEPROM (2-kbit) for Presence Detect (PD). An outline of the HB52E649E12 is 168-pin socket type package (dual lead out). Therefore, the HB52E649E12 makes high density mounting possible without surface mount technology. The HB52E649E12 provides common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the module board.

Features
• Fully compatible with : JEDEC standard outline 8-byte DIMM : Intel PCB Reference design (Rev.1.2)
• 168-pin socket type package (dual lead out)
    - Outline: 133.37 mm (Length) × 43.18 mm (Height) × 4.00 mm (Thickness)
    - Lead pitch: 1.27 mm
• 3.3 V power supply
• Clock frequency: 100 MHZ (max)
• LVTTL interface
• Data BUS width: × 72 ECC
• Single pulsed RAS
• 4 Banks can operates simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length: 1/2/4/8
• 2 variations of burst sequence
    - Sequential
    - Interleave
• Programmable CE latency : 3/4 (HB52E649E12-A6B) : 4 (HB52E649E12-B6B)
• Byte control by DQMB
• Refresh cycles: 8192 refresh cycles/64 ms
• 2 variations of refresh
    - Auto refresh
    - Self refresh

Part Name(s) : HB52F649E1-75B HB52F649E1 Elpida
Elpida Memory, Inc
Description : 512 MB REGISTERED SDRAM DIMM 64-MWORD 72-BIT, 133 MHZ MEMORY BUS, 1-Bank Module (18 pcs of 64 M 4 Components) PC133SDRAM View

Description
The HB52F649E1 belongs to 8-byte DIMM (Dual In-line MEMORY Module) family, and has been developed as an optimized main MEMORY solution for 8-byte processor applications. The HB52F649E1 is a 64M × 72 × 1-bank Synchronous Dynamic RAM REGISTERED Module, mounted 18 pieces of 256-MBit SDRAM (HM5225405BTT) sealed in TSOP package, 1 piece of PLL clock driver, 3 pieces of register driver and 1 piece of serial EEPROM (2-kbit) for Presence Detect (PD). An outline of the HB52F649E1 is 168-pin socket type package (dual lead out). Therefore, the HB52F649E1 makes high density mounting possible without surface mount technology. The HB52F649E1 provides common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the module board.

Features
• Fully compatible with : JEDEC standard outline 8-byte DIMM
• 168-pin socket type package (dual lead out)
    - Outline: 133.35 mm (Length) × 43.18 mm (Height) × 4.00 mm (Thickness)
    - Lead pitch: 1.27 mm
• 3.3 V power supply
• Clock frequency: 133 MHZ (max)
• LVTTL interface
• Data BUS width: × 72 ECC
• Single pulsed RAS
• 4 Banks can operates simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length: 1/2/4/8
• 2 variations of burst sequence
    - Sequential
    - Interleave
• Programmable CE latency : 4 (133 MHZ) : 3 (100 MHZ)
• Byte control by DQMB
• Refresh cycles: 8192 refresh cycles/64 ms
• 2 variations of refresh
    - Auto refresh
    - Self refresh

Part Name(s) : HB52R1289E22-A6B HB52R1289E22-B6B HB52R1289E22 Elpida
Elpida Memory, Inc
Description : 1 GB REGISTERED SDRAM DIMM 128-Mword 72-BIT, 100 MHZ MEMORY BUS, 2-Bank Module (36 pcs of 64 M 4 Components) PC100 SDRAM View

Description
The HB52R1289E22 belongs to 8-byte DIMM (Dual In-line MEMORY Module) family, and has been developed as an optimized main MEMORY solution for 8-byte processor applications. The HB52R1289E22 is a 64M × 72 × 2-bank Synchronous Dynamic RAM Module, mounted 36 pieces of 256-MBit SDRAM (HM5225405BTB) sealed in TCP package, 1 piece of PLL clock driver, 3 pieces register driver and 1 piece of serial EEPROM (2-kbit) for Presence Detect (PD). An outline of the HB52R1289E22 is 168-pin socket type package (dual lead out). Therefore, the HB52R1289E22 makes high density mounting possible without surface mount technology. The HB52R1289E22 provides common data inputs and outputs. Decoupling capacitors are mounted beside TCP on the module board.

Features
• Fully compatible with : JEDEC standard outline 8-byte DIMM : Intel PCB Reference design (Rev. 1.2)
• 168-pin socket type package (dual lead out)
    - Outline: 133.37 mm (length) × 38.10 mm (Height) × 4.80 mm (Thickness)
    - Lead pitch: 1.27 mm
• 3.3 V power supply
• Clock frequency: 100 MHZ (max)
• LVTTL interface
• Data BUS width: × 72 ECC
• Single pulsed RAS
• 4 Banks can operates simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length: 1/2/4/8
• 2 variations of burst sequence
    - Sequential
    - Interleave
• Programmable CE latency : 3/4 (HB52R1289E22-A6B) : 4 (HB52R1289E22-B6B)
• Byte control by DQMB
• Refresh cycles: 8192 refresh cycles/64 ms
• 2 variations of refresh
    - Auto refresh
    - Self refresh

Part Name(s) : HB52RD648DC-B HB52RF648DC-B HB52RF648DC-75B HB52RF648DC-75BL HB52RD648DC-A6B HB52RD648DC-A6BL HB52RD648DC-B6B HB52RD648DC-B6BL Elpida
Elpida Memory, Inc
Description : 512 MB Unbuffered SDRAM S.O.DIMM 64-MWORD 64-bit, 133/100 MHZ MEMORY BUS, 2-Bank Module (16 pcs of 32 M 8 components) PC133/100 SDRAM View

Description
The HB52RF648DC, HB52RD648DC are a 32M × 64 × 2 banks Synchronous Dynamic RAM Small Outline Dual In-line MEMORY Module (S.O.DIMM), mounted 16 pieces of 256-MBit SDRAM (HM5225805BTB) sealed in TCP package and 1 piece of serial EEPROM (2-kbit) for Presence Detect (PD). An outline of the products is 144-pin Zig Zag Dual tabs socket type compact and thin package. Therefore, they make high density mounting possible without surface mount technology. They provide common data inputs and outputs. Decoupling capacitors are mounted beside TCP on the module board.

Features
• Fully compatible with: JEDEC standard outline 8-byte S.O.DIMM
• 144-pin Zig Zag Dual tabs socket type (dual lead out)
    - Outline: 67.60 mm (Length) × 31.75 mm (Height) × 3.80 mm (Thickness)
    - Lead pitch: 0.80 mm
• 3.3 V power supply
• Clock frequency: 133/100 MHZ (max)
• LVTTL interface
• Data BUS width: × 64 Non parity
• Single pulsed RAS
• 4 Banks can operates simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length : 1/2/4/8
• 2 variations of burst sequence
    - Sequential
    - Interleave
• Programmable CE latency: 2/3
• Byte control by DQMB
• Refresh cycles: 8192 refresh cycles/64 ms
• 2 variations of refresh
    - Auto refresh
    - Self refresh
• Low self refresh current: HB52RF648DC-xxBL (L-version) : HB52RD648DC-xxBL (L-version)


Part Name(s) : HB52RF1289E2U HB52RF1289E2U-75B Elpida
Elpida Memory, Inc
Description : 1 GB REGISTERED SDRAM DIMM 128-Mword 72-BIT, 133 MHZ MEMORY BUS, 2-Bank Module (36 pcs of 64 M 4 Components) PC133 SDRAM View

Description
The HB52RF1289E2U belongs to 8-byte DIMM (Dual In-line MEMORY Module) family, and has been developed as an optimized main MEMORY solution for 8-byte processor applications. The HB52RF1289E2U is a 64M × 72 × 2-bank Synchronous Dynamic RAM Module, mounted 36 pieces of 256-MBit SDRAM (HM5225405BTB) sealed in TCP package, 1 piece of PLL clock driver, 3 pieces register driver and 1 piece of serial EEPROM (2-kbit) for Presence Detect (PD). An outline of the HB52RF1289E2U is 168-pin socket type package (dual lead out). Therefore, the HB52RF1289E2U makes high density mounting possible without surface mount technology. The HB52RF1289E2U provides common data inputs and outputs. Decoupling capacitors are mounted beside TCP on the module board.

duct
Features
• Fully compatible with : JEDEC standard outline 8-byte DIMM
• 168-pin socket type package (dual lead out)
    - Outline: 133.35 mm (Length) × 30.48 mm (Height) × 4.80 mm (Thickness)
    - Lead pitch: 1.27 mm
• 3.3 V power supply
• Clock frequency: 133 MHZ (max)
• LVTTL interface
• Data BUS width: × 72ECC
• Single pulsed RAS
• 4 Banks can operates simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length: 1/2/4/8
• 2 variations of burst sequence
    - Sequential
    - Interleave
• Programmable CE latency : 4
• Byte control by DQMB
• Refresh cycles: 8192 refresh cycles/64 ms
• 2 variations of refresh
    - Auto refresh
    - Self refresh

Part Name(s) : HM5257165BTD-75 HM5257165BTD-A6 HM5257805BTD-75 HM5257805BTD-A6 HM5257405BTD-75 HM5257405BTD-A6 Elpida
Elpida Memory, Inc
Description : 512M LVTTL interface SDRAM 133 MHZ/100 MHZ 8-Mword 16-bit 4-bank/16-Mword 8-bit 4-bank /32-Mword 4-bit 4-bank PC/133, PC/100 SDRAM View

Description
The HM5257165B is a 512-MBit SDRAM organized as 8388608-word × 16-bit × 4 bank. The HM5257805B is a 512-MBit SDRAM organized as 16777216-word × 8-bit × 4 bank. The HM5257405B is a 512-MBit SDRAM organized as 33554432-word × 4-bit × 4 bank. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.

Features
• 3.3 V power supply
• Clock frequency: 133 MHZ/100 MHZ (max)
• LVTTL interface
• Single pulsed RAS
• 4 banks can operate simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length: 1/2/4/8
• 2 variations of burst sequence
    - Sequential (BL = 1/2/4/8)
    - Interleave (BL = 1/2/4/8)
• Programmable CAS latency: 2/3
• Byte control by DQM : DQM (HM5257805B/HM5257405B) : DQMU/DQML (HM5257165B)
• Refresh cycles: 8192 refresh cycles/64 ms
• 2 variations of refresh
    - Auto refresh
    - Self refresh
• Temperature range: 0 to 60°C

Part Name(s) : HM5225325F HM5225325F-B60 HM5225645F HM5225645F-B60 HM5225645FBP-B60 HM5225325FBP-B60 Hitachi
Hitachi -> Renesas Electronics
Description : 256M LVTTL interface SDRAM 100 MHZ 1-Mword 64-bit 4-bank/2-Mword 32-bit 4-bank PC/100 SDRAM View

Description
The Hitachi HM5225645F is a 256-MBit SDRAM organized as 1048576-word × 64-bit × 4-bank. The Hitachi HM5225325F is a 256-MBit SDRAM organized as 2097152-word × 32-bit × 4-bank. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 108 bump BGA.

Features
• Single chip wide bit solution (× 64/× 32)
• 3.3 V power supply
• Clock frequency: 100 MHZ (max)
• LVTTL interface
• Extremely small foot print: 1.27 mm pitch
    - Package: BGA (BP-108)
• 4 banks can operate simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length: 4/8/full page
• 2 variations of burst sequence
    - Sequential (BL = 4/8/full page)
    - Interleave (BL = 4/8)
• Programmable CAS latency: 2/3
• Byte control by DQMB

Part Name(s) : HYS64V16220GU HYS64V16220GU-10 HYS64V16220GU-8 HYS64V16220GU-8B HYS64V8200GU HYS64V8200GU-10 HYS64V8200GU-8 HYS64V8200GU-8B HYS72V16220GU HYS72V16220GU-10 HYS72V16220GU-8 HYS72V8200GU HYS72V8200GU-10 HYS72V8200GU-8 PC66-222-920 Infineon
Infineon Technologies
Description : 3.3 V 8M 64/72-BIT 1 Bank SDRAM Module, 3.3 V 16M 64/72-BIT 2 Bank SDRAM Module View

3.3 V 8M × 64/72-BIT 1 Bank SDRAM Module
3.3 V 16M × 64/72-BIT 2 Bank SDRAM Module
168 pin unbuffered DIMM Modules

The HYS 64(72)8200 and HYS 64(72)16220 are industry standard 168-pin 8-byte Dual in-line MEMORY Modules (DIMMs) which are organized as 8M × 64, 8M × 72 in 1 bank and 16M × 64 and 16M × 72 in two banks high speed MEMORY arrays designed with 64M Synchronous DRAMs (SDRAMs) for non-parity and ECC applications. The DIMMs use -8 and -8B speed sort 8M 8 SDRAM devices in TSOP-54 packages to meet the PC100 requirement. Modules which use -10 parts are suitable for PC66 applications only. Decoupling capacitors are mounted on the PC board. The PC board design is according to INTEL’s PC SDRAM Rev. 1.0 module specification.

• 168 Pin PC100-compatible unbuffered 8 Byte Dual-In-Line SDRAM Modules for PC main MEMORY applications
• 1 bank 8M × 64, 8M × 72 and 2 bank 16M × 64, 16M × 72 organization
• Optimized for byte-write non-parity or ECC applications
• JEDEC standard Synchronous DRAMs (SDRAM)
• Fully PC board layout compatible to INTEL’s Rev. 1.0 module specification
• Single + 3.3 V (± 0.3 V ) power supply
• Programmable CAS Latency, Burst Length and Wrap Sequence (Sequential & Interleave)
• Auto Refresh (CBR) and Self Refresh
• Decoupling capacitors mounted on substrate
• All inputs, outputs are LVTTL compatible
• Serial Presence Detect with E2PROM
• Utilizes 8M × 8 SDRAMs in TSOPII-54 packages
• 4096 refresh cycles every 64 ms
• 133.35 mm × 31.75 mm × 4.00 mm card size with gold contact pads

Part Name(s) : HYS64V16220GU HYS64V16220GU-10 HYS64V16220GU-8 HYS64V16220GU-8B HYS64V8200GU HYS64V8200GU-10 HYS64V8200GU-8 HYS64V8200GU-8B HYS72V16220GU HYS72V16220GU-10 HYS72V16220GU-8 HYS72V8200GU HYS72V8200GU-10 HYS72V8200GU-8 PC66-222-920 Siemens
Siemens AG
Description : 3.3 V 8M 64/72-BIT 1 Bank SDRAM Module, 3.3 V 16M 64/72-BIT 2 Bank SDRAM Module View

3.3 V 8M × 64/72-BIT 1 Bank SDRAM Module
3.3 V 16M × 64/72-BIT 2 Bank SDRAM Module
168 pin unbuffered DIMM Modules

The HYS 64(72)8200 and HYS 64(72)16220 are industry standard 168-pin 8-byte Dual in-line MEMORY Modules (DIMMs) which are organized as 8M × 64, 8M × 72 in 1 bank and 16M × 64 and 16M × 72 in two banks high speed MEMORY arrays designed with 64M Synchronous DRAMs (SDRAMs) for non-parity and ECC applications. The DIMMs use -8 and -8B speed sort 8M 8 SDRAM devices in TSOP-54 packages to meet the PC100 requirement. Modules which use -10 parts are suitable for PC66 applications only. Decoupling capacitors are mounted on the PC board. The PC board design is according to INTEL’s PC SDRAM Rev. 1.0 module specification.

• 168 Pin PC100-compatible unbuffered 8 Byte Dual-In-Line SDRAM Modules for PC main MEMORY applications
• 1 bank 8M × 64, 8M × 72 and 2 bank 16M × 64, 16M × 72 organization
• Optimized for byte-write non-parity or ECC applications
• JEDEC standard Synchronous DRAMs (SDRAM)
• Fully PC board layout compatible to INTEL’s Rev. 1.0 module specification
• Single + 3.3 V (± 0.3 V ) power supply
• Programmable CAS Latency, Burst Length and Wrap Sequence (Sequential & Interleave)
• Auto Refresh (CBR) and Self Refresh
• Decoupling capacitors mounted on substrate
• All inputs, outputs are LVTTL compatible
• Serial Presence Detect with E2PROM
• Utilizes 8M × 8 SDRAMs in TSOPII-54 packages
• 4096 refresh cycles every 64 ms
• 133.35 mm × 31.75 mm × 4.00 mm card size with gold contact pads

1

2345678910 Next

All Rights Reserved © datasheetbank.com 2014 - 2019 [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]