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Description : 4-Stage Synchronous Bidirectional Counter

General Description
The AC169 is fully Synchronous 4-Stage up/down Counter. The AC169 is a modulo-16 binary Counter. It features a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the LOW-to-HIGH transition of the Clock.
   
Features
■ ICC reduced by 50%
Synchronous counting and loading
■ Built-In lookahead carry capability
■ Presettable for programmable operation
■ Outputs source/sink 24 mA
   

Fairchild
Fairchild Semiconductor
Description : 4-Stage Synchronous Bidirectional Counter

General Description
The 74F169 is a fully Synchronous 4-Stage up/down Counter. The 74F169 is a modulo-16 binary Counter. Features a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the LOW-to-HIGH transition of the clock.

Features
■ ASynchronous counting and loading
■ Built-in lookahead carry capability
■ Presettable for programmable operation

Description : 4-Stage Synchronous Bidirectional CounterS

4-Stage Synchronous Bidirectional CounterS

The MC54/74F168 and MC54/74F169 are fully Synchronous 4-Stage up/down Counters. The F168 is a BCD decade Counter; the F169 is a modulo-16 binary Counter. Both feature a preset capability for programmable operation, carry lookahead for easy cascading, and a U/D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the LOW-to-HIGH transition of the clock.

• ASynchronous Counting and Loading
• Built-In Lookahead Carry Capability
• Presettable for Programmable Operation

Philips
Philips Electronics
Description : 4-bit Bidirectional binary Synchronous Counter (3-State)

DESCRIPTION
The 74F569 is a fully Synchronous Up/Down binary Counter. It features preset capabilities for programmable operation, carry look ahead for programmable operation, carry look ahead for easy cascading, and U/Dinput to control the direction of counting. For maximum flexibility there are both Synchronous and Master Reset
inputs as well as both Clocked Carry (CC) and Terminal Count (TC) outputs. All state changes except Master Reset are initiated by rising edge of the clock. A High signal on the Output Enable (OE) input forces the output buffers into the high impedance state but does not prevent counting, resetting or parallel loading.

FEATURES
•4-bit Bidirectional counting – binary Counter
Synchronous counting and loading
•Look ahead carry capability for easy cascading
•Preset capability for programmable operation
•Master Reset (MR) overrides all other inputs
Synchronous Reset (SR) overrides counting and parallel loading
•Clock Carry (CC) output to be used as a clock for flip-flops, register and Counters
•3-State outputs for bus organized systems

Description : Synchronous Decade Counter (Direct Clear)/Synchronous 4-bit Binary Counter (Direct Clear)/Synchronous Decade Counter (Synchronous Clear)/Synchronous 4-bit Binary Counter (Synchronous Clear)

Description
The HD74HC160 and the HD74HC162 are 4 bit decade Counters, and the HD74HC161 and the HD74HC163 are 4 bit binary Counters All flip-flops are clocked simultaneously on the low to high to transition (positive edge) of the clock input waveform.
These Counters may be preset using the load input. Presetting ofall four flip-flops is Synchronous to the rising edge of clock. When load is held low counting is disabled and the data on the A, B, C, and D inputs is loaded into the Counter on the rising edge of clock. If the load input is taken high before the positive edge of clock the count operation will be unaffected.

Features
•  High Speed Operation: tpd(Clock to Q) = 18 ns typ (CL= 50 pF)
•  High Output Current: Fanout of 10 LSTTL Loads
•  Wide Operating Voltage: VCC= 2 to 6 V
•  Low Input Current: 1 µA max
•  Low Quiescent Supply Current: ICC(static) = 4 µA max (Ta = 25°C)

Description : Synchronous Decade Counter (Direct Clear)/Synchronous 4-bit Binary Counter (Direct Clear)/Synchronous Decade Counter (Synchronous Clear)/Synchronous 4-bit Binary Counter (Synchronous Clear)

Description
The HD74HC160 and the HD74HC162 are 4 bit decade Counters, and the HD74HC161 and the HD74HC163 are 4 bit binary Counters All flip-flops are clocked simultaneously on the low to high to transition (positive edge) of the clock input waveform.
These Counters may be preset using the load input. Presetting of all four flip-flops is Synchronous to thte rising edge of clock. When load is held low counting is disabled and the data on the A, B, C, and D inputs is loaded into the Counter on the rising edge of clock. If the load input is taken high before the positive edge of clock the count operation will be unaffected.

Features
•  High Speed Operation: tpd(Clock to Q) = 18 ns typ (CL= 50 pF)
•  High Output Current: Fanout of 10 LSTTL Loads
•  Wide Operating Voltage: VCC= 2 to 6 V
•  Low Input Current: 1 µA max

 

Part Name(s) : 4404B
RANDE
R and E International, Inc.
Description : CMOS 8-STAGE BINARY Counter

DESCRIPTION
The 4404B consists of eight Synchronous, single-phase clocked counting stages, with the Q output of each stage accessible. The Counter is reset to all "zeroes" by a high level on the Reset line, Each stage of the Counter utilizes a master-slave flip-flop configuration. The state of the Counter is advance on step in binary order on the negative-going transition of teh input clock pulse.

Part Name(s) : HD74HC668 HD74HC669
Hitachi
Hitachi -> Renesas Electronics
Description : Synchronous UP/Down Decade Counter Synchronous Up/Down 4-bit binary Counter

Description
This Synchronous presettable decade Counter features an internal carry look-ahead for cascading in highspeed counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation helps eliminate the output counting spikes that are normally associated with aSynchronous (ripple-clock) Counters.

Features
• High Speed Operation
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)

Description : 4-bit Synchronous binary Counter with Synchronous reset

DESCRIPTION
The HEF40163B is a fully Synchronous edge-triggered 4-bit binary Counter with a clock input (CP), four Synchronous parallel data inputs (P0 to P3), four Synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP), count enable trickle (CET) and Synchronous reset (SR)), buffered outputs from all four bit positions (O0 to O3) and a terminal count output (TC).

Operation is fully Synchronous and occurs on the LOW to HIGH transition of CP. When PE is LOW, the next LOW to HIGH transition of CP loads data into the Counter from P0 to P3. When PE is HIGH, the next LOW to HIGH transition of CP advances the Counter to its next state only if both CEP and CET are HIGH; otherwise no change occurs in the state of the Counter. TC is HIGH when the state of the Counter is 15 (O0 to O3 = HIGH) and when CET is HIGH. A LOW on SR sets all outputs (O0 to O3 and TC) LOW on the next LOW to HIGH transition of CP, independent of the state of all other Synchronous mode control inputs (CEP, CET and PE). Multistage Synchronous counting is possible without additional components by using a carry look-ahead counting technique; in this case, TC is used to enable successive cascaded stages. CEP, CET, PE and SR must be stable only during the set-up time before the LOW to HIGH transition of CP.

Description : Synchronous UP/Down Decade Counter Synchronous Up/Down 4-bit binary Counter

Description
This Synchronous presettable decade Counter features an internal carry look-ahead for cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation helps eliminate the output counting spikes that are normally associated with aSynchronous (ripple-clock) Counters.

Features
• High Speed Operation
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)

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