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Description : 4-Stage Synchronous Bidirectional Counter

General Description
The AC169 is fully Synchronous 4-Stage up/down Counter. The AC169 is a modulo-16 binary Counter. It features a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the LOW-to-HIGH transition of the Clock.
   
Features
■ ICC reduced by 50%
Synchronous counting and loading
■ Built-In lookahead carry capability
■ Presettable for programmable operation
■ Outputs source/sink 24 mA
   

Fairchild
Fairchild Semiconductor
Description : 4-Stage Synchronous Bidirectional Counter

General Description
The 74F169 is a fully Synchronous 4-Stage up/down Counter. The 74F169 is a modulo-16 binary Counter. Features a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the LOW-to-HIGH transition of the clock.

Features
■ ASynchronous counting and loading
■ Built-in lookahead carry capability
■ Presettable for programmable operation

Description : 4-Stage Synchronous Bidirectional CounterS

4-Stage Synchronous Bidirectional CounterS

The MC54/74F168 and MC54/74F169 are fully Synchronous 4-Stage up/down Counters. The F168 is a BCD decade Counter; the F169 is a modulo-16 binary Counter. Both feature a preset capability for programmable operation, carry lookahead for easy cascading, and a U/D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the LOW-to-HIGH transition of the clock.

• ASynchronous Counting and Loading
• Built-In Lookahead Carry Capability
• Presettable for Programmable Operation

Philips
Philips Electronics
Description : 4-bit Bidirectional binary Synchronous Counter (3-State)

DESCRIPTION
The 74F569 is a fully Synchronous Up/Down binary Counter. It features preset capabilities for programmable operation, carry look ahead for programmable operation, carry look ahead for easy cascading, and U/Dinput to control the direction of counting. For maximum flexibility there are both Synchronous and Master Reset
inputs as well as both Clocked Carry (CC) and Terminal Count (TC) outputs. All state changes except Master Reset are initiated by rising edge of the clock. A High signal on the Output Enable (OE) input forces the output buffers into the high impedance state but does not prevent counting, resetting or parallel loading.

FEATURES
•4-bit Bidirectional counting – binary Counter
Synchronous counting and loading
•Look ahead carry capability for easy cascading
•Preset capability for programmable operation
•Master Reset (MR) overrides all other inputs
Synchronous Reset (SR) overrides counting and parallel loading
•Clock Carry (CC) output to be used as a clock for flip-flops, register and Counters
•3-State outputs for bus organized systems

Description : 8 Stage PRESETTABLE Synchronous DOWN Counter

DESCRIPTION
The M54/74HC40102/40103 are high speed CMOS 8-Stage PRESETTABLE Synchronous DOWN CounterS fabricated with silicon gate C2MOS technology. They achieve the high speed operation similar to equivalent LSTTL while main taining the CMOS low power dissipation.
The HC40102, and HC40103 consist of an 8-Stage Synchronous down Counter with a single output which is active when the internal count is zero. The HC40102 is configured as two cascaded 4-bit BCD Counters, and the HC40103 contains a single 8-bit binary Counter. Each type has control inputs for en abling or disabling the clock, for clearing the Counter to its maximum count, and for presetting the Counter either Synchronously or aSynchronously.

■ HIGH SPEED
   fMAX = 40 MHz (TYP.) at VCC = 5 V
■ LOW POWER DISSIPATION
   ICC = 4 µA (MAX.) at TA = 25 °C
■ HIGH NOISE IMMUNITY
   VNIH = VNIL = 28 % VCC (MIN.)
■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS
■ SYMMETRICAL OUTPUT IMPEDANCE
   |IOH| = IOL = 4 mA (MIN.)
■ BALANCED PROPAGATION DELAYS
   PLH = tPHL
■ WIDE OPERATING VOLTAGE RANGE
   VCC (OPR) = 2 V to 6 V
■ PIN AND FUNCTION COMPATIBLE WITH 40102B/40103B

Part Name(s) : HD14024 HD14024B
Hitachi
Hitachi -> Renesas Electronics
Description : Seven Stage Ripple Counter

Seven Stage Ripple Counter

The HD14024B is a seven Stage ripple Counter with short propagation delays and high maximum clock rates.

Motorola
Motorola => Freescale
Description : 8-BIT Bidirectional BINARY Counter (3-STATE)

8-BIT Bidirectional BINARY Counter (3-STATE)

The MC74F779 is a fully Synchronous 8-Stage up/down Counter with multiplexed 3-state I/O ports for bus-oriented applications. All control functions (hold, count up, count down, Synchronous load) are controlled by two mode pins (S0, S1). The device also features carry look-ahead for easy cascading. All state changes are initiated by the rising edge of the clock.

• Multiplexed 3-State I/O Ports For Bus-oriented Applications
• Built-In Look-Ahead Carry Capability
• Count Frequency 145 MHz Typ
• Supply Current 90 mA Typ
• Fully Synchronous Operation
• Separate Pins for Master Reset and Synchronous Reset
• Center Power Pins to Reduce Effects of Package Inductance
• See F269 for 24-Pin Separate I/O Port Version
• See F579 for 20-Pin Version
• ESD Protection > 4000 Volts

Fairchild
Fairchild Semiconductor
Description : 14-Stage Binary Counter • 12-Stage Binary Counter

General Description
The MM74HC4020, MM74HC4040, are high speed binary ripple carry Counters. These Counters are implemented utilizing advanced silicon-gate CMOS technology to achieve speed performance similar to LS-TTL logic while retaining the low power and high noise immunity of CMOS.
The MM74HC4020 is a 14 Stage Counter and the MM74HC4040 is a 12-Stage Counter. Both devices are incremented on the falling edge (negative transition) of the input clock, and all their outputs are reset to a low level by applying a logical high on their reset input.
These devices are pin equivalent to the CD4020 and CD4040 respectively. All inputs are protected from damage due to static discharge by protection diodes to VCC and ground.

Features
■ Typical propagation delay: 16 ns
■ Wide operating voltage range: 2–6V
■ Low input current: 1 µA maximum
■ Low quiescent current: 80 µA maximum (74HC Series)
■ Output drive capability: 10 LS-TTL loads

 

Description : 14-Stage Binary Counter • 12-Stage Binary Counter

General Description
The MM74HC4020, MM74HC4040, are high speed binary ripple carry Counters. These Counters are implemented utilizing advanced silicon-gate CMOS technology to achieve speed performance similar to LS-TTL logic while retaining the low power and high noise immunity of CMOS.
The MM74HC4020 is a 14 Stage Counter and the MM74HC4040 is a 12-Stage Counter. Both devices are incremented on the falling edge (negative transition) of the input clock, and all their outputs are reset to a low level by applying a logical high on their reset input.
These devices are pin equivalent to the CD4020 and CD4040 respectively. All inputs are protected from damage due to static discharge by protection diodes to VCC and ground.

Features
■ Typical propagation delay: 16 ns
■ Wide operating voltage range: 2–6V
■ Low input current: 1 µA maximum
■ Low quiescent current: 80 µA maximum (74HC Series)
■ Output drive capability: 10 LS-TTL loads

 

Renesas
Renesas Electronics
Description : Synchronous Decade Counter (Synchronous clear)

Synchronous Decade Counter (Synchronous clear)

This Synchronous decade Counter features an internal carry look-ahead for application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs changes coincident with each other when so instructed by the count-enable inputs and internal gating. This mode is operation eliminates the output counting spikes that are normally associated with aSynchronous (ripple clock) Counters. A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. This Counter is fully programmable; that is, the outputs may be preset to either level. As presetting is Synchronous, setting up a low level at the load input disables the Counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input should be avoided when the clock is low if the enable inputs are high at or before the transition.

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