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Part Name(s) : DM74ALS137 DM74ALS137MX DM74ALS137M DM74ALS137N Fairchild
Fairchild Semiconductor
Description : 3 to 8 LINE DECODER/DEMULTIPLEXER WITH ADDRESS LATCHES

General Description
The ALS137 is a three LINE to eight LINE DECODER/DEMULTIPLEXER WITH LATCHES on the three ADDRESS inputs. When the latch-enable input (GL) is LOW, the ALS137 acts as a DECODER/DEMULTIPLEXER. When GL goes from LOW-to-HIGH, the ADDRESS present at the select inputs (A, B, and C) is stored in the LATCHES. Further ADDRESS changes are ignored as long as GL remains HIGH. The output enable controls, G1 and G2, control the state of the outputs independently of the select or latch-enable inputs. All of the outputs are HIGH unless G1 is HIGH and G2 is LOW. The ALS137 is ideally suited for implementing glitch-free DECODERs in strobed (stored-ADDRESS) applications in bus-oriented systems.

Features
■ Combines DECODER and 3-bit ADDRESS latch
■ Incorporates 3 enable inputs to simplify cascading
■ Low power dissipation: 28 mW typ
■ Switching specifications guaranteed over full temperature and VCC range
■ Advanced oxide-isolated, ion-implanted Schottky TTL process

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Part Name(s) : 74HC137U 74HCT137 Philips
Philips Electronics
Description : 3-TO-8 LINE DECODER/DEMULTIPLEXER WITH ADDRESS LATCHES; INVERTING

GENERAL DESCRIPTION
The 74HC/HCT137 are high-speed Si-gate CMOS devices and are pin compatible WITH low power Schottky TTL (LSTTL). They are specified in compliance WITH JEDEC standard no. 7A.

FEATURES
• Combines 3-TO-8 DECODER WITH 3-bit latch
• Multiple input enable for easy expansion or independent controls
• Active LOW mutually exclusive outputs
• Output capability: standard
• ICC category: MSI

 

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Part Name(s) : MM54HC137 MM54HC137J MM74HC137 MM74HC137J MM74HC137N National-Semiconductor
National ->Texas Instruments
Description : 3-TO-8 LINE DECODER WITH ADDRESS LATCHES (Inverted Output)

General Description
This device utilizes advanced silicon-gate CMOS technology, to implement a three-to-eight LINE DECODER WITH LATCHES on the three ADDRESS inputs. When GLgoes from low to high, the ADDRESS present at the select inputs (A, B and C) is stored in the LATCHES. As long as GLremains high no ADDRESS changes will be recognized.

Features
Typical propagation delay: 20 ns
Wide supply range: 2± 6V
Latched inputs for easy interfacing.
Fanout of 10 LS-TTL loads.

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Part Name(s) : 74HC137 74HC137D 74HC137DB 74HC137N Philips
Philips Electronics
Description : 3-TO-8 LINE DECODER, DEMULTIPLEXER WITH ADDRESS LATCHES; INVERTING

General description
The 74HC137 is a high-speed Si-gate CMOS device and is pin compatible WITH low power Schottky TTL (LSTTL). The 74HC137 is specified in compliance WITH JEDEC standard no. 7A.

Features
■ Combines 3-TO-8 DECODER WITH 3-bit latch
■ Multiple input enable for easy expansion or independent controls
■ Active LOW mutually exclusive outputs
■ Low-power dissipation
■ Complies WITH JEDEC standard no. 7A
■ ESD protection:
  ◆ HBM EIA/JESD22-A114-B exceeds 2000 V
  ◆ MM EIA/JESD22-A115-A exceeds 200 V.
■ Multiple package options
■ Specified from −40 °C to +80 °C and from −40 °C to +125 °C.

 

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Part Name(s) : 74HC4515 74HC4515D 74HC4515D,652 74HC4515D,653 74HC4515 74HC4515D 74HC4515D,652 74HC4515D,653 74HC4515DB 74HC4515N 74HC4515N,652 74HC4515N3 74HC4515PW 74HC4515U 74HCT4515 74HCT4515D 74HCT4515D,652 74HCT4515DB 74HCT4515N 74HCT4515N,652 74HCT4515N3 74HCT4515PW 74HCT4515U 74HCT4515D,653 NXP
NXP Semiconductors.
Description : 4-to-16 LINE DECODER/DEMULTIPLEXER WITH input LATCHES; INVERTING

General description
The 74HC4515 is a 4-to-16 LINE DECODER/DEMULTIPLEXER having four binary weighted ADDRESS inputs (A0 to A3) WITH LATCHES, a latch enable input (LE), an enable input (E) and 16 INVERTING outputs (Q0, to Q15).
When LE is HIGH, the selected output is determined by the data on An. When LE goes LOW, the last data present at An are stored in the LATCHES and the outputs remain stable. When E is LOW, the selected output, determined by the contents of the latch, is LOW. When E is HIGH, all outputs are HIGH. The enable input E does not affect the state of the latch. When the device is used as a DEMULTIPLEXER, E is the data input and A0 to A3 are the ADDRESS inputs.
Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

Features and benefits
INVERTING outputs
• CMOS input levels
• 16-LINE demultiplexing capability
• Decodes 4 binary-coded inputs into 16 mutually-exclusive outputs
• Complies WITH JEDEC standard no. 7 A
• ESD protection:
    – HBM JESD22-A114F exceeds 2000 V
    – MM JESD22-A115-A exceeds 200 V
• Specified from -40 °C to +85 °C and -40 °C to +125 °C

Applications
• Digital multiplexing
ADDRESS decoding
• Hexadecimal/BCD decoding

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Part Name(s) : HD74HCT237 HD74HCT237RPEL Renesas
Renesas Electronics
Description : 3-TO-8-LINE DECODER/DEMULTIPLEXER WITH ADDRESS Latch

Description
The HD74HCT137 implements a three-to-eight LINE DECODER WITH LATCHES on the three ADDRESS inputs. When GL goes from low to high, the ADDRESS present at the select inputs (A, B and C) is stored in the LATCHES. As long as GL remains high no ADDRESS changes will be recognized. Output enable controls, G1 and G2, control the state of the outputs independently of the select or latch-enable inputs.

Features
• High Speed Operation: tpd (A, B, C to Y) = 16.5 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 V to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)

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Part Name(s) : HD74HC137 Hitachi
Hitachi -> Renesas Electronics
Description : 3-TO-8-LINE DECODER/DEMULTIPLEXER WITH ADDRESS Latch

Description
The HD74HC137 implements a three-to-eight LINE DECODER WITH LATCHES on the three ADDRESS inputs. When GL goes from low to high, the ADDRESS present at the select inputs (A, B and C) is stored in the LATCHES. As long as GL remains high no ADDRESS changes will be recognized. Output enable controls, G1 and G2, control the state of the outputs independently of the select or latch-enable inputs.

Features
• High Speed Operation: tpd (A, B, C to Y) = 16.5 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 V to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)

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Part Name(s) : HD74HCT137 HD74HCT137FPEL HD74HCT137RPEL Renesas
Renesas Electronics
Description : 3-TO-8-LINE DECODER/DEMULTIPLEXER WITH ADDRESS Latch

Description
The HD74HCT137 implements a three-to-eight LINE DECODER WITH LATCHES on the three ADDRESS inputs. When GL goes from low to high, the ADDRESS present at the select inputs (A, B and C) is stored in the LATCHES. As long as GL remains high no ADDRESS changes will be recognized. Output enable controls, G1 and G2, control the state of the outputs independently of the select or latch-enable inputs.

Features
• High Speed Operation: tpd (A, B, C to Y) = 16.5 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 V to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)

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Part Name(s) : HD74HC137FPEL HD74HC137P HD74HC137RPEL HD74HC137 Renesas
Renesas Electronics
Description : 3-TO-8-LINE DECODER/DEMULTIPLEXER WITH ADDRESS Latch

Description
The HD74HC137 implements a three-to-eight LINE DECODER WITH LATCHES on the three ADDRESS inputs. When GL goes from low to high, the ADDRESS present at the select inputs (A, B and C) is stored in the LATCHES. As long as GL remains high no ADDRESS changes will be recognized. Output enable controls, G1 and G2, control the state of the outputs independently of the select or latch-enable inputs.

Features
• High Speed Operation: tpd (A, B, C to Y) = 16.5 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 V to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)

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Part Name(s) : HD74HCT137 Hitachi
Hitachi -> Renesas Electronics
Description : 3-TO-8-LINE DECODER/DEMULTIPLEXER WITH ADDRESS Latch

Description
The HD74HCT137 implements a three-to-eight LINE DECODER WITH LATCHES on the three ADDRESS inputs. When GL goes from low to high, the ADDRESS present at the select inputs (A, B and C) is stored in the LATCHES. As long as GL remains high no ADDRESS changes will be recognized. Output enable controls, G1 and G2, control the state of the outputs independently of the select or latch-enable inputs.

Features
• LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility
• High Speed Operation: tpd (A, B, C to Y) = 18 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 4.5 to 5.5 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)

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