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Part Name(s) : HM5225325F HM5225325F-B60 HM5225645F HM5225645F-B60 HM5225645FBP-B60 HM5225325FBP-B60 Hitachi
Hitachi -> Renesas Electronics
Description : 256M LVTTL INTERFACE SDRAM 100 MHZ 1-MWORD 64-BIT 4-BANK/2-MWORD 32-BIT 4-BANK PC/100 SDRAM View

Description
The Hitachi HM5225645F is a 256-Mbit SDRAM organized as 1048576-word × 64-BIT × 4-BANK. The Hitachi HM5225325F is a 256-Mbit SDRAM organized as 2097152-word × 32-BIT × 4-BANK. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 108 bump BGA.

Features
• Single chip wide bit solution (× 64/× 32)
• 3.3 V power supply
• Clock frequency: 100 MHZ (max)
LVTTL INTERFACE
• Extremely small foot print: 1.27 mm pitch
    - Package: BGA (BP-108)
• 4 banks can operate simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length: 4/8/full page
• 2 variations of burst sequence
    - Sequential (BL = 4/8/full page)
    - Interleave (BL = 4/8)
• Programmable CAS latency: 2/3
• Byte control by DQMB

Part Name(s) : HM5257165BTD-75 HM5257165BTD-A6 HM5257805BTD-75 HM5257805BTD-A6 HM5257405BTD-75 HM5257405BTD-A6 Elpida
Elpida Memory, Inc
Description : 512M LVTTL INTERFACE SDRAM 133 MHZ/100 MHZ 8-Mword 16-bit 4-BANK/16-Mword 8-bit 4-BANK /32-Mword 4-bit 4-BANK PC/133, PC/100 SDRAM View

Description
The HM5257165B is a 512-Mbit SDRAM organized as 8388608-word × 16-bit × 4 bank. The HM5257805B is a 512-Mbit SDRAM organized as 16777216-word × 8-bit × 4 bank. The HM5257405B is a 512-Mbit SDRAM organized as 33554432-word × 4-bit × 4 bank. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.

Features
• 3.3 V power supply
• Clock frequency: 133 MHZ/100 MHZ (max)
LVTTL INTERFACE
• Single pulsed RAS
• 4 banks can operate simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length: 1/2/4/8
• 2 variations of burst sequence
    - Sequential (BL = 1/2/4/8)
    - Interleave (BL = 1/2/4/8)
• Programmable CAS latency: 2/3
• Byte control by DQM : DQM (HM5257805B/HM5257405B) : DQMU/DQML (HM5257165B)
• Refresh cycles: 8192 refresh cycles/64 ms
• 2 variations of refresh
    - Auto refresh
    - Self refresh
• Temperature range: 0 to 60°C

Part Name(s) : HM5259165B-75 HM5259165B-A6 HM5259165BTD-75 HM5259165BTD-A6 HM5259405B-75 HM5259405B-A6 HM5259405BTD-75 HM5259405BTD-A6 HM5259805B-75 HM5259805B-A6 HM5259805BTD-75 HM5259805BTD-A6 Elpida
Elpida Memory, Inc
Description : 512M LVTTL INTERFACE SDRAM 133 MHZ/100 MHZ 8-Mword 16-bit 4-BANK/16-Mword 8-bit 4-BANK /32-Mword 4-bit 4-BANK PC/133, PC/100 SDRAM View

Description
The HM5259165B is a 512-Mbit SDRAM organized as 8388608-word × 16-bit × 4 bank. The HM5259805B is a 512-Mbit SDRAM organized as 16777216-word × 8-bit × 4 bank. The HM5259405B is a 512-Mbit SDRAM organized as 33554432-word × 4-bit × 4 bank. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.

Features
• 3.3 V power supply
• Clock frequency: 133 MHZ/100 MHZ (max)
LVTTL INTERFACE
• Single pulsed RAS
• 4 banks can operate simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length: 1/2/4/8
• 2 variations of burst sequence
- Sequential (BL = 1/2/4/8)
- Interleave (BL = 1/2/4/8)
• Programmable CAS latency: 2/3
• Byte control by DQM : DQM (HM5259805B/HM5259405B)
                               : DQMU/DQML (HM5259165B)
• Refresh cycles: 8192 refresh cycles/32 ms
• 2 variations of refresh
- Auto refresh
- Self refresh

 

Part Name(s) : HM5225165B-75 HM5225165BLTT-75 HM5225165BLTT-A6 HM5225165BLTT-B6 HM5225165BTT-75 HM5225165BTT-A6 HM5225165BTT-B6 HM5225405B-75 HM5225405BLTT-75 HM5225405BLTT-A6 HM5225405BLTT-B6 HM5225405BTT-75 HM5225405BTT-A6 HM5225405BTT-B6 HM5225805B-75 HM5225805BLTT-75 HM5225805BLTT-A6 HM5225805BLTT-B6 HM5225805BTT-75 HM5225805BTT-A6 HM5225805BTT-B6 HM5225165B-A6 HM5225165B-B6 HM5225805B-A6 HM5225805B-B6 Elpida
Elpida Memory, Inc
Description : 256M LVTTL INTERFACE SDRAM 133 MHZ/100 MHZ 4-Mword 16-bit 4-BANK/8-Mword 8-bit 4-BANK/16-Mword 4-bit 4-BANK PC/133, PC/100 SDRAM View

Description
The HM5225165B is a 256-Mbit SDRAM organized as 4194304-word × 16-bit × 4 bank. The HM5225805B is a 256-Mbit SDRAM organized as 8388608-word × 8-bit × 4 bank. The HM5225405B is a 256-Mbit SDRAM organized as 16777216-word × 4-bit × 4 bank. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.

Features
• 3.3 V power supply
• Clock frequency: 133 MHZ/100 MHZ (max)
LVTTL INTERFACE
• Single pulsed RAS
• 4 banks can operate simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length: 1/2/4/8
• 2 variations of burst sequence
    - Sequential (BL = 1/2/4/8)
    - Interleave (BL = 1/2/4/8)
• Programmable CAS latency: 2/3
• Byte control by DQM : DQM (HM5225805B/HM5225405B) : DQMU/DQML (HM5225165B)
• Refresh cycles: 8192 refresh cycles/64 ms
• 2 variations of refresh
    - Auto refresh
    - Self refresh


Part Name(s) : HM5264165F-75 HM5264165F-A60 HM5264165F-B60 HM5264165FLTT-75 HM5264165FLTT-A60 HM5264165FLTT-B60 HM5264165FTT-75 HM5264165FTT-A60 HM5264165FTT-B60 HM5264405F-75 HM5264405F-A60 HM5264405F-B60 HM5264405FLTT-75 HM5264405FLTT-A60 HM5264405FLTT-B60 HM5264405FTT-75 HM5264405FTT-A60 HM5264405FTT-B60 HM5264805F-75 HM5264805F-A60 HM5264805F-B60 HM5264805FLTT-75 HM5264805FLTT-A60 HM5264805FLTT-B60 HM5264805FTT-75 Elpida
Elpida Memory, Inc
Description : 64M LVTTL INTERFACE SDRAM 133 MHZ/100 MHZ 1-MWORD 16-bit 4-BANK/2-MWORD 8-bit 4-BANK /4-Mword 4-bit 4-BANK PC/133, PC/100 SDRAM View

Description
The HM5264165F is a 64-Mbit SDRAM organized as 1048576-word × 16-bit × 4 bank. The HM5264805F is a 64-Mbit SDRAM organized as 2097152-word × 8-bit × 4 bank. The HM5264405F is a 64-Mbit SDRAM organized as 4194304-word × 4-bit × 4 bank. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.

Features
• 3.3 V power supply
• Clock frequency: 133 MHZ/100 MHZ (max)
LVTTL INTERFACE
• Single pulsed RAS
• 4 banks can operate simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length: 1/2/4/8/full page
• 2 variations of burst sequence
- Sequential (BL = 1/2/4/8/full page)
- Interleave (BL = 1/2/4/8)
• Programmable CAS latency: 2/3
• Byte control by DQM:DQM (HM5264805F/HM5264405F) DQMU/DQML (HM5264165F)
• Refresh cycles: 4096 refresh cycles/64 ms
• 2 variations of refresh
- Auto refresh
- Self refresh
• Full page burst length capability
- Sequential burst
- Burst stop capability

 

Part Name(s) : HM5264165D-B60 HM5264165DLTT-B60 HM5264165DTT-B60 HM5264405D-B60 HM5264405DLTT-B60 HM5264405DTT-B60 HM5264805D-B60 HM5264805DLTT-B60 HM5264805DTT-B60 Hitachi
Hitachi -> Renesas Electronics
Description : 64M LVTTL INTERFACE SDRAM 100 MHZ 1-MWORD x 16-bit x 4-BANK/ 2-Mword x 8-bit x 4-BANK/ 4-Mword x 4-bit x 4-BANK PC/100 SDRAM View
Part Name(s) : HB52E649E12 HB52E649E12-A6B HB52E649E12-B6B Elpida
Elpida Memory, Inc
Description : 512 MB Registered SDRAM DIMM 64-Mword 72-bit, 100 MHZ Memory Bus, 1-Bank Module (18 pcs of 64 M 4 Components) PC100 SDRAM View

Description
The HB52E649E12 belongs to 8-byte DIMM (Dual In-line Memory Module) family, and has been developed as an optimized main memory solution for 8-byte processor applications. The HB52E649E12 is a 64M × 72 × 1-bank Synchronous Dynamic RAM Registered Module, mounted 18 pieces of 256-Mbit SDRAM (HM5225405BTT) sealed in TSOP package, 1 piece of PLL clock driver, 2 pieces of register driver and 1 piece of serial EEPROM (2-kbit) for Presence Detect (PD). An outline of the HB52E649E12 is 168-pin socket type package (dual lead out). Therefore, the HB52E649E12 makes high density mounting possible without surface mount technology. The HB52E649E12 provides common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the module board.

Features
• Fully compatible with : JEDEC standard outline 8-byte DIMM : Intel PCB Reference design (Rev.1.2)
• 168-pin socket type package (dual lead out)
    - Outline: 133.37 mm (Length) × 43.18 mm (Height) × 4.00 mm (Thickness)
    - Lead pitch: 1.27 mm
• 3.3 V power supply
• Clock frequency: 100 MHZ (max)
LVTTL INTERFACE
• Data bus width: × 72 ECC
• Single pulsed RAS
• 4 Banks can operates simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length: 1/2/4/8
• 2 variations of burst sequence
    - Sequential
    - Interleave
• Programmable CE latency : 3/4 (HB52E649E12-A6B) : 4 (HB52E649E12-B6B)
• Byte control by DQMB
• Refresh cycles: 8192 refresh cycles/64 ms
• 2 variations of refresh
    - Auto refresh
    - Self refresh

Part Name(s) : HB52RD648DC-B HB52RF648DC-B HB52RF648DC-75B HB52RF648DC-75BL HB52RD648DC-A6B HB52RD648DC-A6BL HB52RD648DC-B6B HB52RD648DC-B6BL Elpida
Elpida Memory, Inc
Description : 512 MB Unbuffered SDRAM S.O.DIMM 64-Mword 64-BIT, 133/100 MHZ Memory Bus, 2-Bank Module (16 pcs of 32 M 8 components) PC133/100 SDRAM View

Description
The HB52RF648DC, HB52RD648DC are a 32M × 64 × 2 banks Synchronous Dynamic RAM Small Outline Dual In-line Memory Module (S.O.DIMM), mounted 16 pieces of 256-Mbit SDRAM (HM5225805BTB) sealed in TCP package and 1 piece of serial EEPROM (2-kbit) for Presence Detect (PD). An outline of the products is 144-pin Zig Zag Dual tabs socket type compact and thin package. Therefore, they make high density mounting possible without surface mount technology. They provide common data inputs and outputs. Decoupling capacitors are mounted beside TCP on the module board.

Features
• Fully compatible with: JEDEC standard outline 8-byte S.O.DIMM
• 144-pin Zig Zag Dual tabs socket type (dual lead out)
    - Outline: 67.60 mm (Length) × 31.75 mm (Height) × 3.80 mm (Thickness)
    - Lead pitch: 0.80 mm
• 3.3 V power supply
• Clock frequency: 133/100 MHZ (max)
LVTTL INTERFACE
• Data bus width: × 64 Non parity
• Single pulsed RAS
• 4 Banks can operates simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length : 1/2/4/8
• 2 variations of burst sequence
    - Sequential
    - Interleave
• Programmable CE latency: 2/3
• Byte control by DQMB
• Refresh cycles: 8192 refresh cycles/64 ms
• 2 variations of refresh
    - Auto refresh
    - Self refresh
• Low self refresh current: HB52RF648DC-xxBL (L-version) : HB52RD648DC-xxBL (L-version)

Part Name(s) : HB52R1289E22-A6B HB52R1289E22-B6B HB52R1289E22 Elpida
Elpida Memory, Inc
Description : 1 GB Registered SDRAM DIMM 128-Mword 72-bit, 100 MHZ Memory Bus, 2-Bank Module (36 pcs of 64 M 4 Components) PC100 SDRAM View

Description
The HB52R1289E22 belongs to 8-byte DIMM (Dual In-line Memory Module) family, and has been developed as an optimized main memory solution for 8-byte processor applications. The HB52R1289E22 is a 64M × 72 × 2-bank Synchronous Dynamic RAM Module, mounted 36 pieces of 256-Mbit SDRAM (HM5225405BTB) sealed in TCP package, 1 piece of PLL clock driver, 3 pieces register driver and 1 piece of serial EEPROM (2-kbit) for Presence Detect (PD). An outline of the HB52R1289E22 is 168-pin socket type package (dual lead out). Therefore, the HB52R1289E22 makes high density mounting possible without surface mount technology. The HB52R1289E22 provides common data inputs and outputs. Decoupling capacitors are mounted beside TCP on the module board.

Features
• Fully compatible with : JEDEC standard outline 8-byte DIMM : Intel PCB Reference design (Rev. 1.2)
• 168-pin socket type package (dual lead out)
    - Outline: 133.37 mm (length) × 38.10 mm (Height) × 4.80 mm (Thickness)
    - Lead pitch: 1.27 mm
• 3.3 V power supply
• Clock frequency: 100 MHZ (max)
LVTTL INTERFACE
• Data bus width: × 72 ECC
• Single pulsed RAS
• 4 Banks can operates simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length: 1/2/4/8
• 2 variations of burst sequence
    - Sequential
    - Interleave
• Programmable CE latency : 3/4 (HB52R1289E22-A6B) : 4 (HB52R1289E22-B6B)
• Byte control by DQMB
• Refresh cycles: 8192 refresh cycles/64 ms
• 2 variations of refresh
    - Auto refresh
    - Self refresh

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