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Part Name(s) : 74ALVCH16841 74ALVCH16841DGG 74ALVCH16841DL ACH16841DGG Philips
Philips Electronics
Description : 20-BIT BUS INTERFACE D-type LATCH (3-STATE) View

DESCRIPTION
The 74ALVCH16841 has two 10-bit D-type LATCH featuring separate D-type inputs for each LATCH and 3-STATE outputs for BUS oriented applications. The two sections of each register are controlled independently by the LATCH enable (nLE) and output enable (nOE) control gates.

FEATURES
• Wide supply voltage range of 1.2V to 3.6V
• Complies with JEDEC standard no. 8-1A
• Wide supply voltage range of 1.2V to 3.6V
• CMOS low power consumption
• Direct INTERFACE with TTL levels
• MULTIBYTETM flow-through standard pin-out architecture
• Low inductance multiple VCC and GND pins for minimum noise and ground bounce
• Current drive ±24 mA at 3.0 V
• All inputs have BUS hold circuitry
• Output drive capability 50Ω transmission lines @ 85°C
3-STATE non-inverting outputs for BUS oriented applications

 

Part Name(s) : 74ALVT16841 74ALVT16841DGG 74ALVT16841DL AV16841DL AV16841DGG Philips
Philips Electronics
Description : 2.5V/3.3V ALVT 20-BIT BUS INTERFACE LATCH (3-STATE) View

DESCRIPTION
The 74ALVT16841 BUS INTERFACE LATCH is designed to provide extra data width for wider data/address paths of BUSes carrying parity. It is designed for VCC operation at 2.5V or 3.3V with I/O compatibility to 5V.

FEATURES
• High speed parallel LATCHes
• 5V I/O Compatible
• Live insertion/extraction permitted
• Extra data width for wide address/data paths or BUSes carrying parity
• Power-up 3-STATE
• Power-up reset
• Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors
• Output capability: +64mA/–32mA
LATCH-up protection exceeds 500mA per Jedec Std 17
BUS-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs
• ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model

Part Name(s) : 74ABT16841A 74ABTH16841A BH16841ADGG BH16841ADL BT16841ADGG BT16841ADL 74ABT16841ADL 74ABT16841ADGG 74ABTH16841ADL 74ABTH16841ADGG Philips
Philips Electronics
Description : 20-BIT BUS INTERFACE LATCH (3-STATE) View

DESCRIPTION
The 74ABT16841A BUS INTERFACE LATCH is designed to provide extra data width for wider data/address paths of BUSes carrying parity.

FEATURES
• High speed parallel LATCHes
• Live insertion/extraction permitted
• Extra data width for wide address/data paths or BUSes carrying parity
• Power-up 3-STATE
• 74ABTH16841A incorporates BUS-hold data inputs which eliminate the need for external pull-up resistors to hold unused inputs
• Power-up reset
• Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors
• Output capability: +64mA/–32mA
LATCH-up protection exceeds 500mA per Jedec Std 17
• ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model

Part Name(s) : SN74ALS29841 SN74ALS29841DW SN74ALS29841NT TI
Texas Instruments
Description : 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS View

description
This 10-bit LATCH features 3-STATE outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional BUS drivers, and working registers.

3-STATE Buffer-Type Outputs Drive BUS Lines Directly
BUS-Structured Pinout
• Provides Extra BUS-Driving LATCHes Necessary for Wider Address/Data Paths or BUSes With Parity
• Buffered Control Inputs Reduce dc Loading Effects
• Power-Up High-Impedance State
• Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic (NT) 300-mil DIPs


Part Name(s) : CD74FCT843A CD74FCT843AM 74FCT843AM Texas-Instruments
Texas Instruments
Description : BiCMOS 9-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS View

description
The CD74FCT843A is a 9-bit, BUS-INTERFACE, D-type LATCH with 3-STATE outputs, designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional BUS drivers, and working registers.
   
● BiCMOS Technology With Low Quiescent
    Power
● Buffered Inputs
● Noninverted Outputs
● Input/Output Isolation From VCC
● Controlled Output Edge Rates
● 48-mA Output Sink Current
● Output Voltage Swing Limited to 3.7 V
● SCR LATCH-Up-Resistant BiCMOS Process
    and Circuit Design
● Packaged in Plastic Small-Outline Package
   

Part Name(s) : 74ALVCH16843 74ALVCH16843DGG NXP
NXP Semiconductors.
Description : 18-bit BUS-INTERFACE D-type LATCH; 3-STATE View

General description
The 74ALVCH16843 has two 9–bit D-type LATCH featuring separate D-type inputs for each LATCH and 3-STATE outputs for BUS oriented applications.
   
Features and benefits
• Wide supply voltage range of 1.2V to 3.6V
• CMOS low power consumption
• Direct INTERFACE with TTL levels
• Current drive ±24 mA at VCC = 3.0 V.
• MULTIBYTE flow-through standard pin-out architecture
• Low inductance multiple VCC and GND pins
    for minimize noise and ground bounce
• All data inputs have BUShold
• Output drive capability 50 Ω transmission lines at 85 °C
3-STATE non-inverting outputs for BUS oriented applications
• Complies with JEDEC standards:
    – JESD8-5 (2.3 V to 2.7 V)
    – JESD8B/JESD36 (2.7 V to 3.6 V)
• ESD protection:
    – HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V
    – CDM JESD22-C101E exceeds 1000 V
   

Part Name(s) : PI74ALVCH16841A PI74ALVCH16841V PI74ALVCH16841 Pericom-Semiconductor
Pericom Semiconductor
Description : 20-BIT BUS-INTERFACE D-Type LATCH with 3-STATE Outputs View

Product Description
Pericom Semiconductor’s PI74ALVCH series of logic circuits are produced in the Company’s advanced 0.5 micron CMOS technology, achieving industry leading speed.

Product Features
• PI74ALVCH16841 is designed for low voltage operation
• VCC = 2.3V to 3.6V
• Hysteresis on all inputs
• Typical VOLP (Output Ground Bounce)
    < 0.8V at VCC = 3.3V, TA = 25°C
• Typical VOHV (Output VOH Undershoot)
    < 2.0V at VCC = 3.3V, TA = 25°C
BUS Hold retains last active BUS state during 3-STATE, eliminating the need for external pullup resistors
• Industrial operation at –40°C to +85°C
• Packages available:
    - 56-pin 240 mil wide plastic TSSOP (A)
    - 56-pin 300 mil wide plastic SSOP (V)

Part Name(s) : MB2841BB MB2841 Philips
Philips Electronics
Description : Dual 10-bit BUS INTERFACE LATCH (3-STATE) View

DESCRIPTION
The MB2841 BUS INTERFACE register is designed to provide extra data width for wider data/address paths of BUSes carrying parity.
The MB2841 consists of two sets of ten D-type LATCHes with 3-STATE outputs. The flip-flops appear transparent to the data when LATCH Enable (nLE) is High. This allows asynchronous operation, as the output transition follows the data in transition. On the nLE High-to-Low transition, the data that meets the setup and hold time is LATCHed.
Data appears on the BUS when the Output Enable (nOE) is Low. When nOE is High the output is in the High-impedance state.

FEATURES
• High speed parallel LATCHes
• Live insertion/extraction permitted
• Extra data width for wide address/data
   paths or BUSes carrying parity
• Power-up 3-STATE
• Power-up reset
• Ideal where high speed, light loading, or
   increased fan-in are required with MOS microprocessors
• Output capability: +64mA/–32mA
LATCH-up protection exceeds 500mA per Jedec JC40.2 Std 17
• ESD protection exceeds 2000V per MIL
   STD 883 Method 3015 and 200V per Machine Model

Part Name(s) : 74ABT16841A 74ABT16841ADGG 74ABT16841ADGG,112 74ABT16841ADGG,118 74ABT16841ADL 74ABT16841ADL,512 74ABT16841ADL,518 NXP
NXP Semiconductors.
Description : 20-BIT BUS INTERFACE LATCH (3-STATE) View

DESCRIPTION
The 74ABT16841A BUS INTERFACE LATCH is designed to provide extra data width for wider data/address paths of BUSes carrying parity.

FEATURES
• High speed parallel LATCHes
• Live insertion/extraction permitted
• Extra data width for wide address/data paths or BUSes carrying parity
• Power-up 3-STATE
• Power-up reset
• Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors
• Output capability: +64 mA / –32 mA
LATCH-up protection exceeds 500 mA per Jedec Std 17
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model

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