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PERICOM
Pericom Semiconductor Corporation
Description : 18-bit Universal Bus Driver with 3-state Outputs

Product Description
The 18-bit PI74AVC16834 Universal Bus Driver is designed for 1.8V to 3.6V VCC operation.
Data flow from A to Y is controlled by Output Enable (OE). The device operates in the transparent mode when LE is LOW. The A data is latched if CLK is held at a high or low logic level. If LE is HIGH, the A-Bus is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is HIGH, the Outputs are in the high-impedance state.
The PI74AVC16834 Bus Driver is designed to drive an array of 133 MHz synchronous memory chips, with minimal undershoot/overshoot noise, and to meet the input signal rise/fall time requirement of memory chips.

Product Features
• Very high-speed, low-noise Universal Bus Driver with embedded resistor Outputs
• Meets PC133 SDRAM Registered DIMM specification
• Implements output impedance control for low-noise and heavy-load applications
• Fast Propagation Delay: 2.5ns max. for 50pF test load
• VCC = 3.3V or 2.5V or 1.8V
• Packaging (Pb-free & Green available):
    – 56-pin 240 mil wide plastic TSSOP (A)

Part Name(s) : HD74ALVCH16835
Hitachi
Hitachi -> Renesas Electronics
Description : 18-bit Universal Bus Driver with 3-state Outputs

Description
The HD74ALVCH16835 is an 18-bit Universal Bus Driver designed for 2.3 V to 3.6 V VCC operation.

Features
• Supports unregulated battery operation down to 2.7 V
Bus hold on data inputs eliminates the need for external pullup resistors.
• Distrlbuted VCC and GND pin conflguration minimizes high speed switching noise.

Pericom-Semiconductor
Pericom Semiconductor
Description : 18-bit Universal Bus Driver with 3-state Outputs

Product Description
Pericom Semiconductor’s PI74AVC series of logic circuits are produced using the Company’s advanced 0.35 micron CMOS technology, achieving industry leading speed.
The 18-bit PI74AVC16834 Universal Bus Driver is designed for 1.8V to 3.6V VCC operation.

Product Features
• Very high-speed, low-noise Universal Bus Driver with embedded resistor Outputs
• Meets PC133 SDRAM Registered DIMM specification
• Implements output impedance control for low-noise and heavy-load applications
• Fast Propagation Delay: 2.5ns max. for 50pF test load
• VCC = 3.3V or 2.5V or 1.8V
• Packages available:
    ― 56-pin 240 mil wide plastic TSSOP (A)
    ― 56-pin 173 mil wide plastic TVSOP (K)

Part Name(s) : HD74ALVC162835
Hitachi
Hitachi -> Renesas Electronics
Description : 18-bit Universal Bus Driver with 3-state Outputs

Description
The HD74ALVC162835 is an 18-bit Universal Bus Driver designed for 2.3 V to 3.6 V VCC operation.

Features
• Meets “PC SDRAM registered DIMM design support document, Rev. 1.2”
• VCC = 2.3 V to 3.6 V
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±12 mA (@VCC = 3.0 V)
• All Outputs have equivalent 26 Ω series resistors, so no external resistors are required

Hitachi
Hitachi -> Renesas Electronics
Description : 18-bit Universal Bus Driver with 3-state Outputs

Description
The HD74ALVC16835 is an 18-bit Universal Bus Driver designed for 2.3 V to 3.6 V VCC operation. Data flow from A to Y is controlled by output enable (OE). The device operates in the transparent mode when the latch enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip flop on the low to high transition of the CLK. When OE is high, the Outputs are in the high impedance state. To ensure the high impedance state during power up or power down, OE should be tied to VCC through a pullup registor; the minimum value of the registor is determined by the current sinking capability of the Driver.

Features
• Meets “PC SDRAM registered DIMM design support document, Rev. 1.2”
• VCC = 2.3 V to 3.6 V
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±24 mA (@VCC = 3.0 V)

Renesas
Renesas Electronics
Description : 18-bit Universal Bus Driver with 3-state Outputs

Description
The HD74ALVC162835 is an 18-bit Universal Bus Driver designed for 2.3 V to 3.6 V VCC operation. Data flow from A to Y is controlled by the output enable (OE). The device operates in the transparent mode when the latch enable (LE) is high. When LE is low, the A data is latched if the clock (CLK) input is held at a high or low logic level. If the LE is low, the A data is stored in the latch/flip flop on the low to high transition of CLK. When OE is high, the Outputs are in the high impedance state.

Features
• Meets “PC SDRAM registered DIMM design support document, Rev. 1.2”
• VCC = 2.3 V to 3.6 V
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±12 mA (@VCC = 3.0 V)
• All Outputs have equivalent 26 Ω series resistors, so no external resistors are required

Part Name(s) : HD74ALVC162834
Hitachi
Hitachi -> Renesas Electronics
Description : 18-bit Universal Bus Driver with 3-state Outputs and Inverted Latch Enable

Description
The HD74ALVC162834 is an 18-bit Universal Bus Driver designed for 2.3 V to 3.6 V VCC operation.

Features
• Meets “PC SDRAM registered DIMM design support document, Rev. 1.2”
• VCC = 2.3 V to 3.6 V
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±12 mA (@VCC = 3.0 V)
• All Outputs have equivalent 26 Ω series resistors, so no external resistors are required

Description : 18-bit Universal Bus Driver with 3-state Outputs

Description
The HD74ALVC16835 is an 18-bit Universal Bus Driver designed for 2.3 V to 3.6 V VCC operation. Data flow from A to Y is controlled by output enable (OE). The device operates in the transparent mode when the latch enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip flop on the low to high transition of the CLK. When OE is high, the Outputs are in the high impedance state. To ensure the high impedance state during power up or power down, OE should be tied to VCC through a pullup register; the minimum value of the register is determined by the current sinking capability of the Driver.

Features
• Meets “PC SDRAM registered DIMM design support document, Rev. 1.2”
• VCC = 2.3 V to 3.6 V
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±24 mA (@VCC = 3.0 V)
• Ordering Information

Part Name(s) : HD74ALVC16834
Renesas
Renesas Electronics
Description : 18-bit Universal Bus Driver with 3-state Outputs and Inverted Latch Enable

Description
The HD74ALVC16834 is an 18-bit Universal Bus Driver designed for 2.3 V to 3.6 V VCC operation.

Features
• Meets “PC SDRAM registered DIMM design support document, Rev. 1.2”
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±24 mA (@VCC = 3.0 V)

Part Name(s) : HG74ALVC16835C
Hyundai
Hyundai Micro Electronics
Description : 18-bit Universal Bus Driver with 3-state Outputs

General Description
The HG74ALVC16835C is an 18-bit Universal Bus Driver designed for 2.3V to 3.6 V VCC Operation.

Features
● Ideal for Use in PC100 Registered DIMM
● 0.5mm CMOS Technology
● 2.3 ~ 3.6 VCC Operation
● Balanced Output Drive(±24mA)
● Package Options Include Plastic Thin Shrink Small-Outline Packages, Shrink Small-Outline Packages (TSSOP 56 Pins, SSOP 56 Pins, TVSOP56 Pins)

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