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Part Name(s) : HD74ALVCH16835 Hitachi
Hitachi -> Renesas Electronics
Description : 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

Description
The HD74ALVCH16835 is an 18-BIT UNIVERSAL BUS DRIVER designed for 2.3 V to 3.6 V VCC operation.

Features
• Supports unregulated battery operation down to 2.7 V
BUS hold on data inputs eliminates the need for external pullup resistors.
• Distrlbuted VCC and GND pin conflguration minimizes high speed switching noise.

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Part Name(s) : HD74ALVC162835 Hitachi
Hitachi -> Renesas Electronics
Description : 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

Description
The HD74ALVC162835 is an 18-BIT UNIVERSAL BUS DRIVER designed for 2.3 V to 3.6 V VCC operation.

Features
• Meets “PC SDRAM registered DIMM design support document, Rev. 1.2”
• VCC = 2.3 V to 3.6 V
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±12 mA (@VCC = 3.0 V)
• All OUTPUTS have equivalent 26 Ω series resistors, so no external resistors are required

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Part Name(s) : 74ALVC16835 HD74ALVC16835 Hitachi
Hitachi -> Renesas Electronics
Description : 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

Description
The HD74ALVC16835 is an 18-BIT UNIVERSAL BUS DRIVER designed for 2.3 V to 3.6 V VCC operation. Data flow from A to Y is controlled by output enable (OE). The device operates in the transparent mode when the latch enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip flop on the low to high transition of the CLK. When OE is high, the OUTPUTS are in the high impedance state. To ensure the high impedance state during power up or power down, OE should be tied to VCC through a pullup registor; the minimum value of the registor is determined by the current sinking capability of the DRIVER.

Features
• Meets “PC SDRAM registered DIMM design support document, Rev. 1.2”
• VCC = 2.3 V to 3.6 V
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±24 mA (@VCC = 3.0 V)

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Part Name(s) : 74ALVC162835 HD74ALVC162835 Renesas
Renesas Electronics
Description : 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

Description
The HD74ALVC162835 is an 18-BIT UNIVERSAL BUS DRIVER designed for 2.3 V to 3.6 V VCC operation. Data flow from A to Y is controlled by the output enable (OE). The device operates in the transparent mode when the latch enable (LE) is high. When LE is low, the A data is latched if the clock (CLK) input is held at a high or low logic level. If the LE is low, the A data is stored in the latch/flip flop on the low to high transition of CLK. When OE is high, the OUTPUTS are in the high impedance state.

Features
• Meets “PC SDRAM registered DIMM design support document, Rev. 1.2”
• VCC = 2.3 V to 3.6 V
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±12 mA (@VCC = 3.0 V)
• All OUTPUTS have equivalent 26 Ω series resistors, so no external resistors are required

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Part Name(s) : HD74ALVC162834 Hitachi
Hitachi -> Renesas Electronics
Description : 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS and Inverted Latch Enable

Description
The HD74ALVC162834 is an 18-BIT UNIVERSAL BUS DRIVER designed for 2.3 V to 3.6 V VCC operation.

Features
• Meets “PC SDRAM registered DIMM design support document, Rev. 1.2”
• VCC = 2.3 V to 3.6 V
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±12 mA (@VCC = 3.0 V)
• All OUTPUTS have equivalent 26 Ω series resistors, so no external resistors are required

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Part Name(s) : HD74ALVC16835 HD74ALVC16835TEL 74ALVC16835 74ALVC16835TEL Renesas
Renesas Electronics
Description : 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

Description
The HD74ALVC16835 is an 18-BIT UNIVERSAL BUS DRIVER designed for 2.3 V to 3.6 V VCC operation. Data flow from A to Y is controlled by output enable (OE). The device operates in the transparent mode when the latch enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip flop on the low to high transition of the CLK. When OE is high, the OUTPUTS are in the high impedance state. To ensure the high impedance state during power up or power down, OE should be tied to VCC through a pullup register; the minimum value of the register is determined by the current sinking capability of the DRIVER.

Features
• Meets “PC SDRAM registered DIMM design support document, Rev. 1.2”
• VCC = 2.3 V to 3.6 V
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±24 mA (@VCC = 3.0 V)
• Ordering Information

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Part Name(s) : HD74ALVC16834 Renesas
Renesas Electronics
Description : 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS and Inverted Latch Enable

Description
The HD74ALVC16834 is an 18-BIT UNIVERSAL BUS DRIVER designed for 2.3 V to 3.6 V VCC operation.

Features
• Meets “PC SDRAM registered DIMM design support document, Rev. 1.2”
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±24 mA (@VCC = 3.0 V)

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Part Name(s) : HG74ALVC16835C Hyundai
Hyundai Micro Electronics
Description : 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

General Description
The HG74ALVC16835C is an 18-BIT UNIVERSAL BUS DRIVER designed for 2.3V to 3.6 V VCC Operation.

Features
● Ideal for Use in PC100 Registered DIMM
● 0.5mm CMOS Technology
● 2.3 ~ 3.6 VCC Operation
● Balanced Output Drive(±24mA)
● Package Options Include Plastic Thin Shrink Small-Outline Packages, Shrink Small-Outline Packages (TSSOP 56 Pins, SSOP 56 Pins, TVSOP56 Pins)

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Part Name(s) : HD74ALVC16834 Hitachi
Hitachi -> Renesas Electronics
Description : 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS and Inverted Latch Enable

Description
The HD74ALVC16834 is an 18-BIT UNIVERSAL BUS DRIVER designed for 2.3 V to 3.6 V VCC operation.

Features
• Meets “PC SDRAM registered DIMM design support document, Rev. 1.2”
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±24 mA (@VCC = 3.0 V)

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Part Name(s) : 74ALVC162835A HD74ALVC162835A Hitachi
Hitachi -> Renesas Electronics
Description : 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

Description
The HD74ALVC162835A is an 18-BIT UNIVERSAL BUS DRIVER designed for 2.3 V to 3.6 V VCC operation. Data flow from A to Y is controlled by the output enable (OE). The device operates in the transparent mode when the latch enable (LE) is high. When LE is low, the A data is latched if the clock (CLK) input is held at a high or low logic level. If the LE is low, the A data is stored in the latch/flip flop on the low to high transition of CLK. When OE is high, the OUTPUTS are in the high impedance state.

Features
• Supports PC133 and meets “PC SDRAM registered DIMM specification, Rev. 1.1”
• VCC = 2.3 V to 3.6 V
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±12 mA (@VCC = 3.0 V)
• All OUTPUTS have series dumping resistors, so no external resistors are required
• tpd (CLK to Y) = 3.5 ns (Max) (@VCC = 3.3±0.3 V, CL = 50 pF, Ta = 0 to 85°C)
• tpd (CLK to Y) = 2.5 ns (Max) (@VCC = 3.3±0.3 V, CL = 30 pF, Ta = 0 to 85°C)

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