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Philips
Philips Electronics
Description : 16-BIT D-TYPE TRANSPARENT LATCH; 3.6 V tolerant; 3-STATE

DESCRIPTION
The 74AVC16373 is a 16-BIT D-TYPE TRANSPARENT LATCH featuring separate D-TYPE inputs for each LATCH, and 3-STATE OUTPUTS for bus oriented applications. One LATCH Enable (LE) input and one Output Enable (OE) input are provided per 8-bit section. The 74AVC16373 consist of two sections of eight D-TYPE TRANSPARENT LATCHes WITH 3-STATE true OUTPUTS.

FEATURES
• Wide supply voltage range from 1.2 to 3.6 V
• Complies WITH JEDEC standard no. 8-1A/5/7
• CMOS low power consumption
• Input/output tolerant up to 3.6 V
• Dynamic Controlled Output (DCO) circuit dynamically changes output impedance, resulting in noise reduction WITHout speed degradation
• Low inductance multiple VCC and GND pins to minimize noise and ground bounce
• Supports Live Insertion.

NXP
NXP Semiconductors.
Description : 16-BIT D-TYPE TRANSPARENT LATCH; 3.6 V tolerant; 3-STATE

General description
The 74AVC16373 is a 16-BIT D-TYPE TRANSPARENT LATCH featuring separate D-TYPE inputs for each LATCH and 3-STATE OUTPUTS for bus oriented applications. One LATCH enable (LE) input and one output enable (OE) input are provided per 8-bit section. The 74AVC16373 consist of two sections of eight D-TYPE TRANSPARENT LATCHes WITH 3-STATE true OUTPUTS.

Features and benefits
• Wide supply voltage range from 1.2 V to 3.6 V
• Complies WITH JEDEC standards:
    – JESD8-7 (1.2 V to 1.95 V)
    – JESD8-5 (1.8 V to 2.7 V)
    – JESD8-1A (2.7 V to 3.6 V)
• CMOS low power consumption
• Input/output tolerant up to 3.6 V
• Dynamic Controlled Output (DCO) circuit dynamically changes output impedance, resulting in noise reduction WITHout speed degradation
• Low inductance multiple VCC and GND pins to minimize noise and ground bounce
• Supports Live Insertion

Description : 3.3V LVT 16-BIT TRANSPARENT D-TYPE LATCH (3-STATE)

DESCRIPTION
The 74LVT16373A is a high-performance BiCMOS product designed for VCC operation at 3.3V.
This device is a 16-BIT TRANSPARENT D-TYPE LATCH WITH non-inverting 3-STATE bus compatible OUTPUTS. The device can be used as two 8-bit LATCHes or one 16-BIT LATCH. When enable (E) input is High, the Q OUTPUTS follow the data (D) inputs. When enable is taken Low, the Q OUTPUTS are LATCHed at the levels of the D inputs one setup time prior to the High-to-Low transition.

FEATURES
16-BIT TRANSPARENT LATCH
3-STATE buffers
• Output capability: +64mA/-32mA
• TTL input and output switching levels
• Input and output interface capability to systems at 5V supply
• Bus-hold data inputs eliminate the need for external pull-up
   resistors to hold unused inputs
• Live insertion/extraction permitted
• Power-up reset
• Power-up 3-STATE
• No bus current loading when output is tied to 5V bus
LATCH-up protection exceeds 500mA per JEDEC Std 17
• ESD protection exceeds 2000V per MIL STD 883 Method 3015
   and 200V per Machine Model

Description : 16-BIT D-TYPE TRANSPARENT LATCH WITH 5 V tolerant inputs/OUTPUTS; 3-STATE

DESCRIPTION
The 74LVC(H)16373A is a 16-BIT D-TYPE TRANSPARENT LATCH featuring separate D-TYPE inputs for each LATCH and 3-STATE OUTPUTS for bus oriented applications. One LATCH Enable (LE) input and one Output Enable (OE) are provided for each octal. Inputs can be driven from either 3.3 or 5 V devices. In 3-STATE operation, OUTPUTS can handle 5 V. These features allow the use of these devices in a mixed 3.3 and 5 V environment.

FEATURES
• 5 V tolerant inputs/OUTPUTS for interfacing WITH 5 V logic
• Wide supply voltage range from 1.2 to 3.6 V
• CMOS low power consumption
• MULTIBYTE flow-through standard pin-out architecture
• Low inductance multiple power and ground pins for minimum noise and ground bounce
• Direct interface WITH TTL levels
• All data inputs have bushold (74LVCH16373A only)
• High-impedance when VCC = 0 V.
• Complies WITH JEDEC standard no. 8-1A
• ESD protection:
  HBM EIA/JESD22-A114-A exceeds 2000 V
  MM EIA/JESD22-A115-A exceeds 200 V.
• Specified from −40 to +85 °C and −40 to +125 °C.

Description : 2.5V/3.3V 16-BIT D-TYPE TRANSPARENT LATCH (3-STATE)

DESCRIPTION
The 74ALVCH16373 is a 16-BIT D-TYPE TRANSPARENT LATCH featuring separate D-TYPE inputs for each LATCH and 3-STATE OUTPUTS for bus oriented applications. Incorporates bus hold data inputs which eliminate the need for external pull-up or pull-down resistors to hold unused inputs. One LATCH enable (LE) input and one output enable (OE) are provided per 8-bit section.
The 74ALVCH16373 consists of 2 sections of eight D-TYPE TRANSPARENT LATCHes WITH 3-STATE true OUTPUTS. When LE is HIGH, data at the Dn inputs enter the LATCHes. In this condition the LATCHes are TRANSPARENT, i.e., a LATCH output will change each time its corresponding D-input changes.
When LE is LOW the LATCHes store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight LATCHes are available at the OUTPUTS. When OE is HIGH, the OUTPUTS go to the high impedance OFF-state. Operation of the OE input does not affect the state of the LATCHes.

FEATURES
• Wide supply voltage range of 1.2V to 3.6V
• Complies WITH JEDEC standard no. 8-1A
• CMOS low power consumption
• MULTIBYTETM flow-through standard pin-out architecture
• Low inductance multiple VCC and ground pins for minimum noise
   and ground bounce
• Direct interface WITH TTL levels
• All data inputs have bus hold
• Output drive capability 50Ω transmission lines @ 85°C
• Current drive ±24 mA at 3.0 V

Description : 16-BIT D-TYPE TRANSPARENT LATCH; 30 Ω series termination resistors; 5 V tolerant inputs/OUTPUTS; 3-STATE

DESCRIPTION
The 74LVC(H)162373A is a 16-BIT D-TYPE TRANSPARENT LATCH featuring separate D-TYPE inputs for each LATCH and 3-STATE OUTPUTS for bus oriented applications.
   
FEATURES
• 5 V tolerant inputs/OUTPUTS for interfacing WITH 5 V logic
• Wide supply voltage range from 1.2 to 3.6 V
• CMOS low power consumption
• MULTIBYTE flow-through standard pin-out architecture
• Low inductance multiple power and ground pins for
    minimum noise and ground bounce
• Direct interface WITH TTL levels
• All data inputs have bushold (74LVCH162373A only)
• High-impedance when VCC = 0 V
• Complies WITH JEDEC standard no. 8-1A
• ESD protection:
    HBM EIA/JESD22-A114-A exceeds 2000 V
    MM EIA/JESD22-A115-A exceeds 200 V.
• Specified from −40 to +85 °C and −40 to +125 °C.
   

Fairchild
Fairchild Semiconductor
Description : 16-BIT TRANSPARENT LATCH WITH 3-STATE OUTPUTS

General Description
The ACT16373 contains sixteen non-inverting LATCHes WITH 3-STATE OUTPUTS and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear TRANSPARENT to the data when the LATCH Enable (LE) is HIGH. When LE is low, the data that meets the setup time is LATCHed. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the OUTPUTS are in high Z state.

Features
■ Separate control logic for each byte
16-BIT version of the ACT373
OUTPUTS source/sink 24 mA
■ TTL-compatible inputs

Description : 3.3 V 16-BIT TRANSPARENT D-TYPE LATCH; 3-STATE

General description
The 74LVT16373A is a high-performance BiCMOS product designed for VCC operation at 3.3 V.
This device is a 16-BIT TRANSPARENT D-TYPE LATCH WITH non-inverting 3-STATE bus compatible OUTPUTS. The device can be used as two 8-bit LATCHes or one 16-BIT LATCH. When LATCH enable (LE) input is HIGH, the Q OUTPUTS follow the data (D) inputs. When LATCH enable is taken LOW, the Q OUTPUTS are LATCHed at the levels of the D inputs one setup time prior to the HIGH-to-LOW transition.

Features and benefits
16-BIT TRANSPARENT LATCH
3-STATE buffers
• Output capability: +64 mA/–32 mA
• TTL input and output switching levels
• Input and output interface capability to systems at 5 V supply
• Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs
• Live insertion/extraction permitted
• Power-up reset
• Power-up 3-STATE
• No bus current loading when output is tied to 5 V bus
LATCH-up protection:
    • JESD78B Class II exceeds 500 mA
• ESD protection:
    • HBM: JESD22-A114F exceeds 2000 V
    • MM: JESD22-A115-A exceeds 200 V

Description : 2.5 V/3.3 V 16-BIT D-TYPE TRANSPARENT LATCH; 3-STATE

General description
The 74ALVCH16373 is 16-BIT D-TYPE TRANSPARENT LATCH featuring separate D-TYPE inputs for each LATCH and 3-STATE OUTPUTS for bus oriented applications.
Incorporates bus hold data inputs which eliminate the need for external pull-up or pull-down resistors to hold unused inputs.
One LATCH enable (LE) input and one output enable (OE) are provided per 8-bit section.
The 74ALVCH16373 consists of 2 sections of eight D-TYPE TRANSPARENT LATCHes WITH 3-STATE true OUTPUTS. When LE is HIGH, data at the nDn inputs enter the LATCHes. In this condition the LATCHes are TRANSPARENT, therefore a LATCH output will change each time its corresponding D-input changes.
When LE is LOW, the LATCHes store the information that was present at the nDn inputs at a set-up time preceding the LOW-to-HIGH transition of LE. When OE is LOW, the contents of the eight LATCHes are available at the OUTPUTS. When OE is HIGH, the OUTPUTS go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the LATCHes.

Features and benefits
■ Wide supply voltage range from 1.2 V to 3.6 V
■ Complies WITH JEDEC standard JESD8-B
■ CMOS low power consumption
■ MULTIBYTE flow-through standard pin-out architecture
■ Low inductance multiple VCC and GND pins for minimum noise and ground bounce
■ Direct interface WITH TTL levels
■ All data inputs have bus hold
■ Output drive capability 50  transmission lines at 85 C
■ Current drive 24 mA at VCC = 3.0 V

Description : 16-BIT TRANSPARENT LATCH WITH 3-STATE OUTPUTS

General Description
The ACT16373 contains sixteen non-inverting LATCHes WITH 3-STATE OUTPUTS and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear TRANSPARENT to the data when the LATCH Enable (LE) is HIGH. When LE is low, the data that meets the setup time is LATCHed. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the OUTPUTS are in high Z state.

Features
■ Separate control logic for each byte
16-BIT version of the ACT373
OUTPUTS source/sink 24 mA
■ TTL-compatible inputs

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