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Description : 3.3V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP (3-STATE)

DESCRIPTION
The 74LVT16374A is a high-performance BiCMOS product designed for VCC operation at 3.3V. This device is a 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP featuring non-inverting 3-STATE OUTPUTS. The device can be used as two 8-bit FLIP-FLOPs or one 16-BIT FLIP-FLOP. On the positive transition of the clock (CP), the Q OUTPUTS of the FLIP-FLOP take on the logic levels set up at the D inputs.

FEATURES
16-BIT EDGE-TRIGGERED FLIP-FLOP
3-STATE buffers
• Output capability: +64mA/-32mA
• TTL input and output switching levels
• Input and output interface capability to systems at 5V supply
• Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs
• Live insertion/extraction permitted
• Power-up reset
• Power-up 3-STATE
• No bus current loading when output is tied to 5V bus
• Latch-up protection exceeds 500mA per JEDEC Std 17
• ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model

Philips
Philips Electronics
Description : 16-BIT edge triggered D-TYPE FLIP-FLOP; 3.6 V tolerant; 3-STATE

DESCRIPTION
The 74AVC16374 is a 16-BIT edge triggered FLIP-FLOP featuring separate D-TYPE inputs for each FLIP-FLOP and 3-STATE OUTPUTS for bus oriented applications. The 74AVC16374 consist of 2 sections of eight edge triggered FLIP-FLOPs. A clock input (CP) and an output enable (OE) are provided per 8-bit section.

FEATURES
• Wide supply voltage range from 1.2 to 3.6 V
• Complies WITH JEDEC standard no. 8-1A/5/7
• CMOS low power consumption
• Input/output tolerant up to 3.6 V
• DCO (Dynamic Controlled Output) circuit dynamically changes output impedance, resulting in noise reduction WITHout speed degradation
• Low inductance multiple VCC and GND pins to minimize noise and ground bounce
• Supports Live Insertion.

Description : 2.5V/3.3V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP (3-STATE)

DESCRIPTION
The 74ALVT16374 is a high-performance BiCMOS product designed for VCC operation at 2.5V or 3.3V WITH I/O compatibility up to 5V.
This device is a 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP featuring non-inverting 3-STATE OUTPUTS. The device can be used as two 8-bit FLIP-FLOPs or one 16-BIT FLIP-FLOP. On the positive transition of the clock (CP), the Q OUTPUTS of the FLIP-FLOP take on the logic levels set up at the D inputs.

FEATURES
16-BIT EDGE-TRIGGERED FLIP-FLOP
• 5V I/O compatibile
3-STATE buffers
• Output capability: +64mA/-32mA
• TTL input and output switching levels
• Input and output interface capability to systems at 5V supply
• Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs
• Live insertion/extraction permitted
• Power-up reset
• Power-up 3-STATE
• No bus current loading when output is tied to 5V bus
• Latch-up protection exceeds 500mA per JEDEC Std 17
• ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model

 

Description : 16-BIT edge triggered D-TYPE FLIP-FLOP WITH 5 Volt tolerant inputs/OUTPUTS (3-STATE)

DESCRIPTION
The 74LVC(H)16374A is a 16-BIT EDGE-TRIGGERED FLIP-FLOP featuringseparate D-TYPE inputs for each FLIP-FLOP and 3-STATE OUTPUTS for bus oriented applications. The 74LVC16374A consists of 2 sections of eight positive EDGE-TRIGGERED FLIP-FLOPs. A clock (CP) input and an output enable (OE) are provided for each octal. Inputs can be driven from either 3.3V or 5V devices. In 3-STATE operation, OUTPUTS can handle 5V. These features allow the use of these devices in a mixed 3.3V/5V environment.

FEATURES
• 5 volt tolerant inputs/OUTPUTS for interfacing WITH 5V logic
• Wide supply voltage range of 1.2 V to 3.6 V
• Complies WITH JEDEC standard no. 8-1A
• CMOS low power consumption
• MULTIBYTETM flow-through standard pin-out architecture
• Low inductance multiple power and ground pins for minimum noise and ground bounce
• Direct interface WITH TTL levels
• All data inputs have bus hold (74LVCH16374A only)
• High impedance when VCC = 0

Description : 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP; 3-STATE

General description
The 74ALVT16374 is a high performance BiCMOS product designed for VCC operation at 2.5 V or 3.3 V WITH I/O compatibility up to 5 V.
This device is a 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP featuring non-inverting 3-STATE OUTPUTS. The device can be used as two 8-bit FLIP-FLOPs or one 16-BIT FLIP-FLOP. On the positive transition of the clock (CP), the Q OUTPUTS of the FLIP-FLOP take on the logic levels set up at the D inputs.

Features
16-BIT EDGE-TRIGGERED FLIP-FLOP
■ 5 V I/O compatible
3-STATE buffers
■ Output capability: +64 mA and −32 mA
■ TTL input and output switching levels
■ Input and output interface capability to systems at 5 V supply
■ Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs
■ Live insertion and extraction permitted
■ Power-up reset
■ Power-up 3-STATE
■ No bus current loading when output is tied to 5 V bus
■ Latch-up protection exceeds 500 mA per JESD78
■ Electrostatic discharge protection:
    ◆ MIL STD 883 method 3015: exceeds 2000 V
    ◆ Machine model: exceeds 200 V

Pericom-Semiconductor
Pericom Semiconductor
Description : 16-BIT Edge Triggered D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

Product Description
Pericom Semiconductors PI74ALVCH series of logic circuits are produced in the Companys advanced 0.5 micron CMOS technology, achieving industry leading speed.
This 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP is designed for 2.3V to 3.6V VCC operation.
The PI74ALVCH16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit FLIP-FLOPs or one 16-BIT FLIP-FLOP. On the positive transition of the Clock (CLK) input, the Q OUTPUTS of the FLIP-FLOP take on the logic levels set up at the data (D) inputs. OE can be used to place the eight OUTPUTS in either a normal logic state (high or low logic levels) or a high impedance state. In that state, the OUTPUTS neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines WITHout need for interface or pullup components. OE does not affect internal operations of the FLIP-FLOP. Old data can be retained or new data can be entered while the OUTPUTS are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

Product Features
• PI74ALVCH16374 is designed for low voltage operation
• VCC = 2.3V to 3.6V
• Hysteresis on all inputs
• Typical VOLP (Output Ground Bounce)
   < 0.8V at VCC = 3.3V, TA = 25°C
• Typical VOHV (Output VOH Undershoot)
   < 2.0V at VCC = 3.3V, TA = 25°C
• Bus Hold retains last active bus state during 3-STATE
   eliminating the need for external pullup resistors
• Industrial operation at -40°C to +85°C
• Packages available:
   - 48-pin 240 mil wide plastic TSSOP (A)
   - 48-pin 300 mil wide plastic SSOP (V)

Description : 2.5V/3.3V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP (3-STATE)

DESCRIPTION
The 74ALVCH16374 is a 16-BIT EDGE-TRIGGERED FLIP-FLOP featuring separate D-TYPE inputs for each FLIP-FLOP and 3-STATE OUTPUTS for bus oriented applications. Incorporates bus hold data inputs which eliminate the need for external pull-up or pull-down resistors to hold unused inputs. The 74ALVCH16374 consists of 2 sections of eight EDGE-TRIGGERED FLIP-FLOPs. A clock (CP) input and an output enable (OE) are provided per 8-bit section.

FEATURES
• Wide supply voltage range of 1.2 V to 3.6 V
• Complies WITH JEDEC standard no. 8-1A
• CMOS low power consumption
• MULTIBYTETM flow-through standard pin-out architecture
• Low inductance multiple VCC and ground pins for minimum noise and ground bounce
• Direct interface WITH TTL levels
• All data inputs have bushold
• Output drive capability 50Ω transmission lines @ 85°C
• Current drive ±24 mA at 3.0 V

Description : Dual 4-bit D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH clear (3-STATE)
Dual 4-bit D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH clear (3-STATE)
Description : 2.5 V/3.3 V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP; 3-STATE

General description
The 74ALVCH16374 is 16-BIT EDGE-TRIGGERED FLIP-FLOP featuring separate D-TYPE inputs for each FLIP-FLOP and 3-STATE OUTPUTS for bus oriented applications. Incorporates bus hold data inputs which eliminate the need for external pull-up or pull-down resistors to hold unused inputs.

Features and benefits
■ Wide supply voltage range from 1.2 V to 3.6 V
■ Complies WITH JEDEC standard JESD8-B
■ CMOS low power consumption
■ MULTIBYTE flow-through standard pin-out architecture
■ Low inductance multiple VCC and GND pins for minimum noise and ground bounce
■ Direct interface WITH TTL levels
■ All data inputs have bus hold
■ Output drive capability 50  transmission lines at 85 C
■ Current drive 24 mA at VCC = 3.0 V

Description : 3.3 V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP; 3-STATE

General description
The 74LVT16374A; 74LVTH16374A are high performance BiCMOS products designed for VCC operation at 3.3 V. This device is a 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP featuring non-inverting 3-STATE OUTPUTS. The device can be used as two 8-bit FLIP-FLOPs or one 16-BIT FLIP-FLOP. On the positive transition of the clock (nCP), the nQn OUTPUTS of the FLIP-FLOP take on the logic levels set up at the nDn inputs.

Features and benefits
16-BIT EDGE-TRIGGERED FLIP-FLOP
3-STATE buffers
● Output capability: +64 mA and −32 mA
● TTL input and output switching levels
● Input and output interface capability to systems at 5 V supply
● Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs
● Live insertion and extraction permitted
● Power-up reset
● Power-up 3-STATE
● No bus current loading when output is tied to 5 V bus
● Latch-up protection:
   ● JESD78B Class II exceeds 500 mA
● ESD protection:
   ● HBM JESD22-A114F exceeds 2000 V
   ● MM JESD22-A115-A exceeds 200 V

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