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Part Name(s) : WED3EG6417S-D4 WED3EG6417S262D4 WED3EG6417S265D4 WED3EG6417S202D4 WEDC
White Electronic Designs Corporation
Description : 128MB - 16Mx64 DDR SDRAM UNBUFFERED View

DESCRIPTION
The WED3DG6417S is a 16Mx64 Double Data Rate SDRAM memory module based on 128MB DDR SDRAM component. The module consists of eight 16Mx8 DDR SDRAMs in 66 pin TSOP package mounted on a 200 pin FR4 Substrate.
Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lenths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

FEATURES
■ Double-data-rate architecture
■ Bi-directional data strobes (DQS)
■ Differential clock inputs (CK & CK#)
■ Programmable Read Latency 2,2.5 (clock)
■ Programmable Burst Length (2,4,8)
■ Programmable Burst type (sequential & interleave)
■ Edge aligned data output, center aligned data input
■ Auto and self refresh
■ Serial presence detect
■ JEDEC standard 200 pin SO-DIMM package
■ Power supply: 2.5V ± 0.25V

Part Name(s) : WED3EG6418S-D4 WED3EG6418S335D4 WED3EG6418S262D4 WED3EG6418S265D4 WED3EG6418S202D4 WEDC
White Electronic Designs Corporation
Description : 128MB- 16Mx64 DDR SDRAM UNBUFFERED W/PLL View

DESCRIPTION
The WED3DG6418S is a 16Mx64 Double Data Rate SDRAM memory module based on 128MB DDR SDRAM component. The module consists of eight 16Mx8 DDR SDRAMs in 66 pin TSOP package mounted on a 200 Pin FR4 substrate.
Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lenths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

FEATURES
■ Double-data-rate architecture
■ Speed of 100MHz, 133MHz and 166MHz
■ Bi-directional data strobes (DQS)
■ Differential clock inputs (CK & CK#)
■ Programmable Read Latency 2,2,5 (clock)
■ Programmable Burst Length (2,4,8)
■ Programmable Burst type (sequential & interleave)
■ Edge aligned data output, center aligned data input
■ Auto and self refresh
■ Serial presence detect
■ JEDEC standard 200 pin SO-DIMM package
■ Power Supply: 2.5V ± 0.25V

Part Name(s) : PLL103-02 PLL103-02XI PLL103-02XC PLL103-02XM ETC1
Unspecified
Description : DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS View

[PLL]

DESCRIPTIONS
The PLL103-02 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS or to support 2 unbuffered standard SDRAM DIMMS and 2 DDR DIMMS. The PLL103-02 can be used in conjunction with the PLL202-04 or similar clock synthesizer for the VIA Pro 266 chipset. The PLL103-02 also has an I2C interface, which can enable or disable each output clock. When power up, all output clocks are enabled (has internal pull up).

FEATURES
• Generates 24 output buffer from one input.
• Supports up to four DDR DIMMS or 2 SDRAM DIMMS.
• Supports 266MHz DDR SDRAM.
• One additional output for feedback.
• Less than 5ns delay.
• Skew between any outputs is less than 100 ps.
• 2.5V or 3.3V Supply range.
• Enhanced DDR and SDRAM Output Drive selected by I2C.
• Available in 48 pin SSOP.

Part Name(s) : ICS93718 ICS93718YFLFT AV93718 AV93718YFLFT IDT
Integrated Device Technology
Description : DDR and SDRAM Buffer View

Description
DDR & SDRAM fanout buffer, for VIA Pro 266, KT266 and P4X266 DDR chipsets

Output Features
• Low skew, fanout buffer
• 1 to 12 differential clock distribution
• I2C for functional and output control
• Feedback pin for input to output synchronization
• Supports up to 4 DDR DIMMs or 3 SDRAM DIMMs + 2 DDR DIMMs
• Frequency supports up to 200MHz (DDR400)
• Supports Power Down Mode for power mananagement
• CMOS level control signal input


Part Name(s) : ICS93725 ICS93725YFT ICST
Integrated Circuit Systems
Description : DDR and SDRAM Zero Delay Buffer View

Product Description/Features:
• Low skew, Zero Delay Buffer
• 1 to 13 SDRAM PC133 clock distribution
• 1 to 6 pairs of DDR clock distribution
• I2C for functional and output control
• Separate feedback path for both memory mode to adjust synchronization.
• Supports up to 2 DDR DIMMs or 3 SDRAM DIMMs
• Frequency support for up to 200MHz
• Individual I2C clock stop for power mananagement
• CMOS level control signal input

Recommended Application:
    DDR & SDRAM Zero Delay Buffer for SIS 635/640/645/650 & 735/740/746 style chipsets.

Part Name(s) : M312L2828ET0 M312L3223ETS M312L6420ETS M312L6423ETS M383L2828ET1 M383L3223ETS M383L6420ETS M383L6423ETS Samsung
Samsung
Description : DDR SDRAM Registered Module View

184pin Registered Module based on 256Mb E-die (x4, x8) with 1,700 / 1,200mil Height & 72-bit ECC

 

256MB, 32M x 72 ECC Module (M383(12)L3223ETS) (Populated as 1 bank of x8 DDR SDRAM Module)

512MB, 64M x 72 ECC Module (M383(12)L6423ETS) (Populated as 2 bank of x8 DDR SDRAM Module)

512MB, 64M x 72 ECC Module (M383(12)L6420ETS) (Populated as 1 bank of x4 DDR SDRAM Module)

1GB, 128M x 72 ECC Module [M383(12)L2828ET1(0)] (Populated as 2 bank of x4 DDR SDRAM Module)

 

 

Part Name(s) : EBD11UD8ABFB EBD11UD8ABFB-6B EBD11UD8ABFB-7A EBD11UD8ABFB-7B EBD11UD8ABFB-6A Elpida
Elpida Memory, Inc
Description : 1GB Unbuffered DDR SDRAM DIMM View

Description
The EBD11UD8ABFB is 128M words ×64 bits, 2 banks Double Data Rate (DDR) SDRAM unbuffered
module, mounted 16 pieces of 512M bits DDR SDRAM sealed in TSOP package.

 

Part Name(s) : PLL103-02XC-R PLL103-02XI-R PLL
PhaseLink Corporation
Description : DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS View

DESCRIPTION
The PLL103-02 is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 can be used in conjunction with a clock synthesizer for the VIA Pro 266 chipset. The PLL103-02 also has an I2C interface, which can enable or disable each output clock. When powered up, all output clocks are enabled (have internal pull ups).

FEATURES
• Generates 24 output buffers from one input.
• Supports up to four DDR DIMMS.
• Supports 266MHz DDR SDRAM.
• One additional output for feedback.
• Less than 5ns delay.
• Skew between any outputs is less than 100 ps.
• 2.5V Supply range.
• Enhanced DDR Output Drive selected by I2C.
• Available in 48 pin SSOP.

Part Name(s) : NT256D72S89AKGU NT256D72S89AKGU-7K NT256D72S89AKGU-75B NT256D72S89AKGU-8B Nanya
Nanya Technology
Description : 184pin Low Profile Registered DDR SDRAM MODULE Based on 32Mx8 DDR SDRAM View

Description
NT256D72S89AKGU is a Low Profile Registered 184-Pin 1U Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM), organized as a one-bank 32Mx72 high-speed memory array. The module uses nine 32Mx8 DDR SDRAMs in 400 mil TSOP II packages. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All NANYA 184 DDR SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long space-saving footprint.

Features
• 184-Pin 1U Registered 8-Byte Dual In-Line Memory Module
• 32Mx72 Double Data Rate (DDR) SDRAM DIMM
• Performance:
• Intended for 100 MHz and 133 MHz applications
• Inputs and outputs are SSTL-2 compatible
• VDD = 2.5Volt ± 0.2, VDDQ = 2.5Volt ± 0.2
SDRAMs have 4 internal banks for concurrent operation
• Differential clock inputs
• Data is read or written on both clock edges
• Bi-directional data strobe with one clock cycle preamble and one-half clock post-amble
• ADDRess and control signals are fully synchronous to positive clock edge
• Programmable Operation:
    - Device CAS Latency: 2, 2.5
    - Burst Type: Sequential or Interleave
    - Burst Length: 2, 4, 8
    - Operation: Burst Read and Write
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 13/10/1 ADDRessing (row/column/bank)
• 7.8 µs Max. Average Periodic Refresh Interval
• Serial Presence Detect
• Gold contacts
SDRAMs in 66-pin TSOP Type II Package

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