datasheetbank_Logo     Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

P/N + Description + Content Search

Search Words :

Part Name(s) : HCC40147B HCF40147B HCC40147BF HCF40147BM1 HCF40147BEY HCF40147BC1 ST-Microelectronics
STMicroelectronics
Description : 10 TO 4 LINE BCD PRIORITY ENCODER View

DESCRIPTION
The HCC/HCF40147B CMOS ENCODER features PRIORITY encoding of the inputs TO ensure that only the highest order data LINE is encoded. Ten data input LINEs (0-9) are encoded TO four LINE (8, 4, 2, 1) BCD. The highest PRIORITY LINE is LINE 9. All four output LINEs are logic 1 (VSS) when all input LINEs are logic 0. All inputs and outputs are buffered, and each output can drive one TTL Low Power Schottky load. The HCC/HCFF40147 is functionally similar TO the T54/T74LS147 if pin 15 is tied low.

■ ENCODES 10 LINE TO 4 LINE BCD
■ ACTIVE LOW INPUTS AND OUTPUTS
■ STANDARDIZED, SYMMETRICAL OUTPUT CHARACTERIZATION
100 % TESTED FOR QUIESCENT CURRENT AT 20 V
■ 5V, 10V AND 15V PARAMETRIC RATINGS
■ MAXIMUM INPUT CURREENT OF 1 µA AT 18V OVER FULL PACKAGE TEMPERATURE RANGE; 100 nA AT 18 V AND 25 oC
■ NOISE MARGIN (FULL PACKAGE TEMPERATURE RANGE): 1V AT VDD = 5V, 2V AT VDD = 10V, 2.5V AT VDD = 15V

APPLICATIONS:
■ KEYBOARD ENCODING
10 LINE TO BCD ENCODING
■ RANGE SELECTION

Part Name(s) : CD4014 CD40147BE CD40147BEE4 CD40147BM CD40147BM96 CD40147BM96E4 CD40147BME4 CD40147BMS CD40147BMT CD40147BMTE4 CD40147BNSR CD40147BNSRE4 CD40147BPW CD40147BPWE4 CD40147BPWR CD40147BPWRE4 Intersil
Intersil
Description : 10 LINE TO 4 LINE BCD PRIORITY ENCODER View

Description
CD40147BMS CMOS ENCODER features PRIORITY encoding of the inputs TO ensure that only the highest order data LINE is encoded. Ten data input LINEs (0-9) are encoded TO four LINE (8,4, 2, 1) BCD. The highest PRIORITY LINE is LINE 9. All four output LINEs are logic 1 (VSS) when all input LINEs are logic 0. All inputs and outputs are buffered, and each output can drive one TTL low power Schottky load. The CD40147BMS is func tionally similar TO the TTL 54/74147 if pin 15 is tied low.

Features
• High Voltage Type (20V Rating)
• Encodes 10 LINE TO 4 LINE BCD
• Active Low Inputs and Outputs
100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Pack age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V
• Standardized Symmetrical Output Characteristics
• Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices”

Applications
• Keyboard Encoding
10 LINE TO BCD Encoding
• Range Selection

Part Name(s) : HCF40147B HCF40147BEY HCF40147BM1 HCF40147M013TR STMICROELECTRONICS
STMicroelectronics
Description : 10 TO 4 LINE BCD PRIORITY ENCODER View

DESCRIPTION
HCF40147B is a monolithic integrated circuit fabricated in Metal Oxide SemiconducTOr technology available in DIP and SOP packages.
HCF40147B, ENCODER CMOS, features PRIORITY encoding of the inputs TO ensure that only the highest order data LINE is encoded. Ten data input LINEs (0-9) are encoded TO four LINE (8, 4, 2, 1) BCDs.

■ ENCODES 10 LINE TO 4 LINE BCD
■ ACTIVE LOW INPUTS AND OUTPUTS
■ STANDARDIZED, SYMMETRICAL OUTPUT CHARACTERIZATION
■ QUIESCENT CURRENT SPECIFIED UP TO 20V
■ 5V, 10V AND 15V PARAMETRIC RATINGS
■ MAXIMUM INPUT CURRENT OF 1 µA AT 18V OVER FULL PACKAGE TEMPERATURE RANGE; 100 nA AT 18 V AND 25°C
■ NOISE MARGIN (FULL PACKAGE TEMPERATURE RANGE): 1V AT VDD =5V, 2V AT VDD =10V, 2.5V AT VDD = 15V
■ INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C
100% TESTED FOR QUIESCENT CURRENT
■ MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES"

Part Name(s) : HD74HC149 Renesas
Renesas Electronics
Description : 8-TO-8-LINE PRIORITY ENCODER View

Description
The HD74HC149 is PRIORITY ENCODER which has 8 input LINEs (0 - 7) and 8 output lies (Y0 - Y7).
It is the logical combination of a HD74HC148 8-3 LINE PRIORITY ENCODER driving a HD74HC138 3-8 LINE decoder.
Only one request output can be low at a time. The output that is low is dependent on the highest PRIORITY request that is low. The order of PRIORITY is 7 highest and 0 lowest.

Features
• High Speed Operation: tpd (0 - 7 TO Y) = 16 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 TO 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)


Part Name(s) : M54HC147 M74HC147 M54HC147F1R M74HC147M1R M74HC147B1R M74HC147C1R ST-Microelectronics
STMicroelectronics
Description : 10 TO 4 LINE PRIORITY ENCODER View

DESCRIPTION
The M54/74HC147 is a high speed CMOS 10 TO 4 LINE PRIORITY ENCODER fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption.
This device features PRIORITY encoding of the inputs TO ensure that only the highest order data LINE is encoded. Nine input LINEs are encoded TO a four LINE BCD output. The implied decimal zero condition requires no input condition as zero is encoded when all nine dataLINEsare athigh logic level. Alldata input and outputs are active at the low logic level. All in puts are equipped with protection circuits against static discharge and transient excess voltage.

■ HIGH SPEED
   tPD = 15 ns (TYP.) at VCC = 5 V
■ LOW POWER DISSIPATION
   ICC = 4 µA (MAX.) at TA = 25 °C
■ HIGH NOISE IMMUNITY
   VNIH = VNIL = 28 % VCC (MIN.)
■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS
■ SYMMETRICAL OUTPUT IMPEDANCE
IOH = IOL = 4 mA (MIN.)
■ BALANCED PROPAGATION DELAYS
   tPLH = tPHL
■ WIDE OPERATING VOLTAGE RANGE
   VCC (OPR) = 2 V TO 6 V
■ PIN AND FUNCTION COMPATIBLE WITH 54/74LS147

Part Name(s) : MC54F148 MC54F148J MC74F148 MC74F148D MC74F148N Motorola
Motorola => Freescale
Description : 8-LINE TO 3-LINE PRIORITY ENCODER View

8-LINE TO 3-LINE PRIORITY ENCODER FAST™ SHOTTKY TTL

The MC54/74F148 provides three bits of binary coded output representing the position of the highest order active input, along with an output indicating thepresence of anyactive input. It is easily expanded via input and output enables TO provide PRIORITY encoding over many bits.


• Encodes Eight Data LINEs in PRIORITY
• Provides 3-Bit Binary PRIORITY Code
• Input Enable Capability
• Signals When Data Present on Any Input
• Cascadable for PRIORITY Encoding of n Bits

Part Name(s) : SN54LS147 SN54LS147J SN54LS148 SN54LS148J SN54LS74 SN54LS748 SN54LS748J SN74LS147 SN74LS147D SN74LS147N SN74LS148 SN74LS148D SN74LS148N SN74LS748 SN74LS748D SN74LS748N Motorola
Motorola => Freescale
Description : 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS LOW POWER SCHOTTKY View

10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS

The SN54/74LS147 and the SN54/74LS148 are PRIORITY ENCODERs. They provide PRIORITY decoding of the inputs TO ensure that only the highest order dataLINE is encoded.Both devices have data inputs and outputs which are active at the low logic level.
TheLS147 encodes nine data LINEs TO four-LINE (8-4-2-1) BCD. The implied decimalzero condition does not require an input condition because zero is encoded when all nine data LINEs are at a high logic level.
TheLS148 encodes eight data LINEs TO three-LINE (4-2-1)binary (octal). By providingcascading circuitry (Enable Input EI and Enable Output EO) octal expansion is allowed without needing external circuitry.

 

 

Part Name(s) : 74F148 N74F148D N74F148N Philips
Philips Electronics
Description : 8-input PRIORITY ENCODER View

DESCRIPTION
The 74F148 8-input PRIORITY ENCODER accepts data from eight active-Low inputs and provides a binary representation on the three active-Low outputs. A PRIORITY is assigned TO each input so that when two or more inputs are simultaneously active, the input with the highest PRIORITY is represented on the output, with input LINE I7 having the highest PRIORITY.

FEATURES
•Code conversions
•Multi-channel D/A converter
•Decimal-TO-BCD converter
•Cascading for PRIORITY encoding of “N” bits
•Input enable capability
PRIORITY encoding-auTOmatic selection of highest PRIORITY input LINE
•Output enable-active Low when all inputs are High
•Group signal output-active when any input is Low

Part Name(s) : 5962F9863301V9A 5962F9863301VCC 5962F9863301VXC ACS147D/SAMPLE-03 ACS147DMSR-03 ACS147HMSR-03 ACS147K/SAMPLE-03 ACS147KMSR-03 ACS147MS Intersil
Intersil
Description : Radiation Hardened 10-TO-4 LINE PRIORITY ENCODER View

Radiation Hardened 10-TO-4 LINE PRIORITY ENCODER

These nine-input PRIORITY ENCODERs accept data from nine active LOW inputs and provide a binary representation on the four active LOW outputs. A PRIORITY is assigned TO each input so that when two or more inputs are simultaneously active, the input with the highest PRIORITY is represented on the output. Input LINE I9 has the highest PRIORITY.

Features
• QML Qualified Per MIL-PRF-38535 Requirements
• 1.25 Micron Radiation Hardened SOS CMOS
• Radiation Environment
- Latch-Up Free Under Any Conditions
- TOtal Dose (Max.) . . . . . . . . . . . . . . . . . 3 x 105 RAD(Si)
- SEU Immunity . . . . . . . . . . . . . <1 x 10 -10 Errors/Bit/Day
- SEU LET Threshold . . . . . . . . . . . . >100MeV/(mg/cm2)
• Input Logic Levels. . . . VIL= (0.3)(VCC), VIH= (0.7)(VCC)
• Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . ±12mA (Min)
• Quiescent Supply Current . . . . . . . . . . . . . . . 20µA (Max)
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . .17ns (Max)

Applications
• High Speed Control Circuits
• Sensor MoniTOring
• Low Power Designs

1

2345678910 Next

All Rights Reserved © datasheetbank.com 2014 - 2020 [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]