datasheetbank_Logo    Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site
Part Name  

P/N + Description + Content Search

Search Words :

Part Name(s) : FAN1654 FAN1654MTF FAN1654MTFX FAN1654M FAN1654MX Fairchild
Fairchild Semiconductor
Description : 1.5A LDO, DDR BUS TERMINATION REGULATOR

Description
The FAN1654 is a low-cost bi-directional LDO specifically designed for terminating DDR memory BUS. It can both sink and source up to 1A continuous, 1.5A peak, providing enough current for most DDR applications. Load regulation meets the JEDEC spec, VTT = (VDDQ/2) ± 40mV.

Features
• Sinks and sources 1A continuous, 1.5A peak
• -40°C to +125°C Operating Range
• Load regulation: (VDDQ/2) ± 40mV
• 5mA VREF buffer tracks VTT
• On-chip thermal limiting
• Power-enhanced eTSSOP™-16 package
• Low Current Shutdown Mode
• Output Short Circuit Protection

Applications
DDR terminators

View
Part Name(s) : CM3107 CM3107-00SB CM3107-12SH CM3107-00SH CM3107-00SN CM310701S CM3107-00SM CALMIRCO
California Micro Devices Corp
Description : 2 Amp Source/ Sink BUS TERMINATION REGULATOR for DDR Memory and Front Side BUS Applications

Product Description
The CM3107 is a sinking and sourcing REGULATOR specifically designed for series-parallel BUS TERMINATION for high-speed chip set BUSses as well as DDR memory systems. It can source and sink current up to 2.0A with a load regulation of 0.5%. The VTT output voltage is selectable by VDDQSEL and FSBSEL pins. The VDDQSEL pin controls whether the CM3107 is in DDR memory mode with VTT=VDDQ/2, or in FSB mode. In FSB mode, FSBSEL controls whether VTT is 1.225V or 1.45V. This allows the same chip to be used in two different circuits on an Intel 865-based motherboard.

Features
• Ideal for Intel 865 Front Side BUS VTT and DDR VTT applications
• Sinks and sources 2 Amps
• Over current protection
• Over temperature protection
• Integrated power MOSFETs
• Excellent accuracy (0.5% load regulation)
• Selectable output (1.225V/1.45V or VDDQ/2)
• 8-lead SOIC and PSOP packages
• Lead-free versions available

Applications
• Intel 865/845 Front Side BUS TERMINATION
• Single and dual DDR memory TERMINATION
• Active TERMINATION BUSes
• Graphics card DDR memory TERMINATION

View
Part Name(s) : FAN6550 Fairchild
Fairchild Semiconductor
Description : 2A DDR BUS TERMINATION REGULATOR

Description
The FAN6550 switching REGULATOR is designed to convert voltage supplies ranging from 2.3V to 4V into a desired output voltage or TERMINATION voltage for DDR SDRAM memory. The FAN6550 can be implemented to produce regulated output voltages in two different modes. In the default mode, when the VREF pin is open, the FAN6550 output voltage is 50% of the voltage applied to VCCQ. The FAN6550 can also be used to produce various user-defined voltages by forcing a voltage on the VREFIN pin. In this case, the output voltage follows the input VREFIN voltage. The switching REGULATOR is capable of sourcing or sinking up to 2A of current while regulating an output VTT voltage to within 3% or less. Transient output currents of ±3A can also be accommodated.

Features
• Can source and sink up to 2A continous, 3A peak
• No heatsink required
• Integrated Power MOSFETs
• Generates TERMINATION voltages for DDR SDRAM
• VREF input available for external voltage divider
• Separate voltages for VCCQ and PVDD
• Buffered VREF output
• VOUT of ±3% or less at 2A
• Minimum external components
• 0°C to 70°C operating range
• Shutdown for standby or suspend mode operation
• Thermal Shutdown ≈ 130ºC

View
Part Name(s) : FAN6555 FAN6555M FAN6555MX Fairchild
Fairchild Semiconductor
Description : 2A DDR BUS TERMINATION REGULATOR

Description
The FAN6555 switching REGULATOR is designed to convert voltage supplies ranging from 2.3V to 4V into a desired output voltage or TERMINATION voltage for DDR SDRAM memory. The FAN6555 can be implemented to produce regulated output voltages in two different modes. In the default mode, when the VREFpin is open, the FAN6555 output voltage is 50% of the voltage applied to VCCQ.

Features
• Can source and sink up to 2A continous, 3A peak
• No heatsink required
• Integrated Power MOSFETs
• Generates TERMINATION voltages for DDR SDRAM
• VREF input available for external voltage divider
• Separate voltages for VCCQand PVDD
• Buffered VREF output
• VOUT of ±3% or less at 2A
• Minimum external components
• 16-pin SOIC package
• -40°C to +85°C operating temperature range
• Shutdown for standby or suspend mode operation
• Thermal Shutdown ≈130ºC

View
Part Name(s) : LP2996 LP2996LQ LP2996LQX LP2996M LP2996MR LP2996MRX LP2996MX National-Semiconductor
National ->Texas Instruments
Description : DDR TERMINATION REGULATOR

General Description
The LP2996 linear REGULATOR is designed to meet the JEDEC SSTL-2 specifications for TERMINATION of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM TERMINATION. The LP2996 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.

Features
Source and sink current
Low output voltage offset
No external resistors required
Linear topology
Suspend to Ram (STR) functionality
Low external component count
Thermal Shutdown
Available in SO-8, PSOP-8 or LLP-16 packages

Applications
DDR-I and DDR-II TERMINATION Voltage
SSTL-2 and SSTL-3 TERMINATION
HSTL TERMINATION

View
Part Name(s) : W83310S W83310SG Winbond
Winbond
Description : BUS TERMINATION REGULATOR With Over Temp. & Current Limit

GENERAL DESCRIPTION
The W83310S is a linear REGULATOR which provides achieves continuous 1.8 Amp bi-directional sinking
and driving capability for DDR SDRAM BUS terminator application.

FEATURES
Regulates a bi-directional power with driving and sinking capability
Provides achieve continuous 1.8Amp driving and sinking current
Power MOSFET integrated
Low external component count
Low output voltage offset
Operates with +3.3V and +2.5V control power
Current limit protection
Over temperature protection
Power package SOP-8
Low cost and easy to use

APPLICATIONS
DDR and DDR II BUS TERMINATION REGULATOR
Active TERMINATION BUS
SSTL-2
SSTL-3

View
Part Name(s) : LP2994 LP2994M LP2994MX National-Semiconductor
National ->Texas Instruments
Description : DDR TERMINATION REGULATOR

General Description
The LP2994 REGULATOR is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications (Series Stub TERMINATION Logic) for active TERMINATION of DDR SDRAM. The device utilizes an internal operational amplifier to provide linear regulation of VTT without the need for expensive external components. The output stage prevents shoot through while delivering 1.5A continuous current and maintaining excellent load regulation. The LP2994 also in corporates an active low shutdown pin to tri-state the output during Suspend To Ram (STR) states.

Features
■ Source and sink current
■ Low external component count
■ Independent analog and power rails
■ Linear topology
■ Small package SO-8
■ Low cost and easy to use
■ Shutdown pin

Applications
■ SSTL-2
■ SSTL-3
DDR-SDRAM TERMINATION
DDR-II TERMINATION

 

View
Part Name(s) : RT9005A RT9005B RT9005APSP RT9005BPSP RT9005AGSP RT9005BGSP Richtek
Richtek Technology
Description : DDR VDDQ and TERMINATION Voltage REGULATOR

General Description
The RT9005A/B is a dual-output linear REGULATOR for DDRSDRAM VDDQ supply and TERMINATION voltage VTT supply.
The REGULATOR is capable of actively sinking or sourcing up to 2A. The output TERMINATION voltage can be tightly regulated to track 1/2 VDDQ by two external voltage divider resistors.

Features
• Ideal for DDR-I and DDR-II VDDQ, VTT Applications
• Integrated Power MOSFETs
• Generates TERMINATION Voltage for SSTL_2, SSTL _18, HSTL, SCSI-2 and SCSI-3 Interfaces
• High Accuracy Output Voltage at Full-Load
• VOUT2 Sink and Source 2A Continuous Current
• VOUT2 Adjustment by Two External Resistors
• Shutdown for Suspend to RAM (STR) Functionality with High-Impedance Output
• Current Limiting Protection
• On-Chip Thermal Protection
• Available in SOP-8 (Exposed Pad) Packages
• RoHS Compliant and 100% Lead (Pb)-Free

Applications
• Desktop PCs, Notebooks, and Workstations
• Graphics Card Memory TERMINATION
• Set Top Boxes, Digital TVs, Printers
• Embedded Systems
• Active TERMINATION BUSes
DDR-I and DDR-II Memory Systems

View
Part Name(s) : TPS51200 TPS51200DRCR TPS51200DRCRG4 TPS51200DRCT TPS51200DRCTG4 TPS51200DRC TI
Texas Instruments
Description : Sink and Source DDR TERMINATION REGULATOR

Description
The TPS51200 device is a sink and source double data rate (DDR) TERMINATION REGULATOR specifically designed for low input voltage, low-cost, low-noise systems where space is a key consideration.
The TPS51200 maintains a fast transient response and requires a minimum output capacitance of only 20 μF. The TPS51200 supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, DDR3L, Low-Power DDR3 and DDR4 VTT BUS TERMINATION.
In addition, the TPS51200 provides an open-drain PGOOD signal to monitor the output regulation and an EN signal that can be used to discharge VTT during S3 (suspend to RAM) for DDR applications.
The is available in the thermally efficient 10-pin VSON thermal pad package, and is rated both Green and Pb-free. It is specified from –40°C to +85°C.

Features
• Input Voltage: Supports 2.5-V Rail and 3.3-V Rail
• VLDOIN Voltage Range: 1.1 V to 3.5 V
• Sink and Source TERMINATION REGULATOR Includes
   Droop Compensation
• Requires Minimum Output Capacitance of 20-μF
   (Typically 3 × 10-μF MLCCs) for Memory
   TERMINATION Applications (DDR)
• PGOOD to Monitor Output Regulation
• EN Input
• REFIN Input Allows for Flexible Input Tracking
   Either Directly or Through Resistor Divider
• Remote Sensing (VOSNS)
• ±10-mA Buffered Reference (REFOUT)
• Built-in Soft Start, UVLO, and OCL
• Thermal Shutdown
• Supports DDR, DDR2, DDR3, DDR3L, Low
   Power DDR3, and DDR4 VTT Applications
• 10-Pin VSON Package With Thermal Pad

Applications
• Memory TERMINATION REGULATOR for DDR, DDR2,
   DDR3, DDR3L, Low-Power DDR3 and DDR4
• Notebooks, Desktops, and Servers
• Telecom and Datacom
• Base Stations
• LCD-TVs and PDP-TVs
• Copiers and Printers
• Set-Top Boxes

View
Part Name(s) : W83310G-R2 W83310S-R2 Winbond
Winbond
Description : BUS TERMINATION REGULATOR

GENERAL DESCRIPTION
The W83310S-R2 is a linear REGULATOR which provides achieves peak 2.0 Amp/cont. 1.8 Amp bidirectional sinking and driving capability for DDR SDRAM BUS terminator application.

FEATURES
Regulates a bi-directional power with driving and sinking capability
Provides achieve peak 2.0 Amp/cont. 1.8 Amp driving and sinking current
Power MOSFET integrated
Low external component count
Low output voltage offset
Operates with +3.3V and +2.5V control power
Small package
Low cost and easy to use

APPLICATIONS
DDR BUS TERMINATION REGULATOR
Active TERMINATION BUS
SSTL-2
SSTL-3

View

1

2345678910 Next

 

All Rights Reserved © datasheetbank.com 2014 - 2019 [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]