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Part Name(s) : V385 V385AG V385AGLFT_ V385AGLF_ V385AGT V385GLF V385GLFT ICST
Integrated Circuit Systems
Description : 8-BIT LVDS TRANSMITTER FOR VIDEO View

General Description
The V385 transmitter converts 28 bits of 3.3 V CMOS/TTL into 4 Low Voltage Differential Signaling (LVDS) Data streams while the transmit clock input is transmitted in parallel with the Data streams over a fifth LVDS link. The V385 can be programmed for Rising Edge or falling Edge clocks through pin R_FB.
ICS manufactures a large variety of video application devices. Consult ICS for all of your video application requirements.

Features
• Pin and function compatible with the National
   DS90C385, TI SN65LVDS93 and THine THC63LVDM83
• Convert 28 bits of 3.3 V CMOS/TTL into 4 LVDS streams
• Up to 2.38 Gbps throughput or 297.5 Megabytes/sec bandwidth
• Wide clock frequency range from 20 MHz to 85 MHz
• Spread spectrum compatible
• Supports VGA, SVGA, XGA, and SXGA
LVDS voltage swing of 350 mV for low EMI
• On-chip PLL requires no external components
• Single 3.3 V low-power CMOS design
• Programmable Rising or falling Edge Strobe
• Power-down control function
• Compatible with TIA/EIA-644 LVDS standards
• Packaged in a 56-pin TSSOP (Pb free available)

Part Name(s) : V385AGLF V385AGLFT V385A ICST
Integrated Circuit Systems
Description : 8-BIT LVDS TRANSMITTER FOR VIDEO View

General Description
The V385A transmitter converts 28 bits of 3.3 V CMOS/TTL into 4 Low Voltage Differential Signaling (LVDS) Data streams while the transmit clock input is transmitted in parallel with the Data streams over a fifth LVDS link.
Compared to the V385, the V385A provides an extended clock frequency range of 12-90 MHz, rather than 20-85 MHz. Other performance improvements have been incorporated as well.
The V385A can be programmed for Rising Edge or falling Edge clocks through pin R_FB.

Features
• Extended clock frequency range of 12 to 90 MHz
• Pin and function compatible with the National
   DS90C385, TI SN65LVDS93 and THine
   THC63LVDM83, but with extended clock frequency
   and operating temperature range
• Convert 28 bits of 3.3 V CMOS/TTL into 4 LVDS streams
• Up to 2.52 Gbps throughput or 315 Megabytes/sec bandwidth
• Spread spectrum compatible
• Supports SD, HD and VGA graphics applications
LVDS voltage swing of 350 mV for low EMI
• On-chip PLL requires no external components
• Single 3.3 V low-power CMOS design
• Operating temperature of 0 to +70°C
• Programmable Rising or falling Edge Strobe
• Power-down control function
• Compatible with TIA/EIA-644 LVDS standards
• Packaged in a 56-pin TSSOP (Pb free available)

Part Name(s) : FIN3383 FIN3384 FIN3385 FIN3386 FIN3383MTD FIN3384MTD FIN3385MTD FIN3386MTD Fairchild
Fairchild Semiconductor
Description : Low Voltage 28-Bit Flat Panel Display Link Serializers/Deserializers View

General Description
The FIN3385 and FIN3383 transform 28 bit wide parallel LVTTL (Low Voltage TTL) Data into 4 serial LVDS (Low Voltage Differential Signaling) Data streams. A phaselocked transmit clock is transmitted in parallel with the Data stream over a separate LVDS link. Every cycle of transmit clock 28 bits of input LVTTL Data are sampled and transmitted.

Features
■ Low power consumption
■ 20 MHz to 85 MHz shift clock support
■ r1V common-mode range around 1.2V
■ Narrow bus reduces cable size and cost
■ High throughput (up to 2.38 Gbps throughput)
■ Internal PLL with no external component
■ Compatible with TIA/EIA-644 specification
■ Devices are offered 56-lead TSSOP packages

Part Name(s) : FIN3385MTDX FIN3386MTDX Fairchild
Fairchild Semiconductor
Description : Low-Voltage, 28-Bit, Flat-Panel Display Link Serializer / Deserializer View

Description
The FIN3385 and FIN3386 transform 28-Bit wide parallel Low-Voltage TTL (LVTTL) Data into four serial Low Voltage Differential Signaling (LVDS) Data streams. A phase-locked transmit clock is transmitted in parallel with the Data stream over a separate LVDS link. Every cycle of transmit clock, 28-Bits of input LVTTL Data are sampled and transmitted.
The FIN3386 receives and converts the 4/3 serial LVDS Data streams back into 28/21 bits of LVTTL Data, acting as the deserializer.

Features
Operation -40°C to +85°C
Low Power Consumption
20MHz to 85MHz Shift Clock Support
±1V Common-Mode Range around 1.2V
Narrow Bus Reduces Cable Size and Cost
High Throughput (up to 2.38Gbps)
Internal PLL with No External Component
Compatible with TIA/EIA-644 Specification
56-Lead, TSSOP Package


Part Name(s) : NT7181 NT7181F NT7181FQ ETC
Unspecified
Description : LVDS Transmitter 24 Bit Color Host-LCD Display Panel Interface View

[NOVATEK]

General Description
The NT7181 transmitter contains four 7-bit parallel-load serial-out registers, a 7x clock synthesizer, and five low-voltage differential (LVDS) line in a single integrated circuit. These functions allow 28 bits of single-ended low-voltage TTL (LVTTL) Data to be synchronously transmitted over four balanced-pair conductors for receipt by a compatible receiver, such as the DS90CF386 or THC63LVDF84A.The NT7181 transmitter is offered with programmable Edge Data Strobes for convenient interface with a variety of graphic controllers. The NT7181 transmitter can be programmed for Rising Edge Strobe(RFB=1) or falling Edge Strobe(RFB=0) through the RFB pin. When transmitting, Data bits D0 - D27 are each loaded into registers of the NT7181 on the Rising Edge or falling Edge of the input clock signal (CLKIN). The frequency of CLKIN is multiplied seven times and then used to unload the Data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (TCLK) are then output to LVDS output drivers. The frequency of TCLK is the same as the input clock, CLKIN.
The NT7181 requires no external components and little or no control. The Data bus appears the same at the input to the transmitting and output of the receiver with the Data transmission transparent to the user. The only user intervention is the possible use of the shutdown/clear ( PWDN ) active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low level on this signal clears all internal registers to a low level. The NT7181 are characterized for operation over free-air temperature ranges of 0°C to 70°C.

Features
■ 28:4 Data Channel Compression at up to 297 Megabytes per Second Throughput
■ Suited for VGA, SVGA, XGA and Dual pixel SXGA, UXGA Display Data Transmission From Controller to Display With Very Low EMI
■ 28 Data Channels and Clock-In Low-Voltage TTL and 4 Data Channels and Clock-Out Low-Voltage Differential
■ Operates From a Single 3.3V Supply With 250mW (Typ)
■ Low profile 56 Lead TSSOP Package
■ Clock Edge Programmable for Transmitter
■ Wide Phase-Lock Input Frequency Range: 25 MHz To 85 MHz
■ Supports Spread Spectrum Clock Generator
■ Suggests to use for LCD monitor only
■ No External Components Required for PLL

Part Name(s) : MAX9268 MAX9268GCM MAX9268GCM/V+ MAX9268GCM/V+T MAX9268GCM/V MAX9268GCM/V-T MaximIC
Maxim Integrated
Description : Gigabit Multimedia Serial Link Deserializer with LVDS System Interface View

General Description
The MAX9268 deserializer utilizes Maxim’s gigabit multimedia serial link (GMSL) technology. The MAX9268 deserializer features an LVDS system interface for reduced pin count and a smaller package, and pairs with any GMSL serializer to form a complete digital serial link for joint transmission of high-speed video, audio, and bidirectional control Data.

Features
♦ Pairs with Any GMSL Serializer
♦ 2.5Gbps Payload-Rate AC-Coupled Serial Link
♦ Scrambled 8b/10b Line Coding
♦ Supports WXGA (1280 x 800) with 24-Bit Color
♦ 8.33MHz to 104MHz (3-Channel LVDS) or 6.25MHz to 78MHz (4-Channel LVDS) Output Clock
♦ 4-Bit to 32-Bit Word Length, 8kHz to 192kHz I2S Audio Channel Supports High-Definition Audio
♦ Embedded Half-/Full-Duplex Bidirectional Control Channel (100kbps to 1Mbps)
♦ Two 3-Level Inputs Support 9 Device Addresses
♦ Interrupt Supports Touch-Screen Functions for Display Panels
♦ I2C Master for Peripherals
♦ Equalizer for Serial Link Input
♦ Programmable Spread Spectrum on the LVDS and Control Outputs for Reduced EMI
♦ Serial-Data Clock Recovery Eliminates an External Clock
♦ Automatic Data-Rate Detection Allows On-the-Fly Data-Rate Change
♦ Built-In PRBS Generator for BER Testing of the Serial Link
♦ ISO 10605 and IEC 61000-4-2 ESD Protection
♦ -40NC to +105NC Operating Temperature Range
♦ 1.8V to 3.3V I/O and 3.3V Core Supplies
♦ Patent Pending

Applications
    High-Resolution Automotive Navigation
    Rear-Seat Infotainment
    Megapixel Camera Systems

Part Name(s) : THC63LVD823 THINE
THine Electronics, Inc.
Description : Single(135MHz)/Dual(170MHz) Link LVDS Transmitter for SXGA/SXGA+/UXGA View

General Description
The THC63LVD823 transmitter is designed to support Single Link transmission between Host and Flat Panel Display up to SXGA+ resolutions and Dual Link transmission between Host and Flat Panel Display up to UXGA resolutions.
   
Features
• Wide dot clock range: 25-135MHz suited for VGA,
    SVGA, XGA, SXGA, SXGA+ and UXGA
• PLL requires No external components
• Supports Dual Link, Dual-in (TTL)/Dual-out
    (LVDS) pixel up to 170MHz dot clock for UXGA
• Supports Single Link, Dual-in (TTL)/Single-out
    (LVDS) pixel up to 135MHz dot clock for SXGA+
• Supports Single Link, Single-in (TTL)/Single-out
    (LVDS) pixel up to 85MHz dot clock for XGA
• Clock Edge selectable
• Supports Reduced swing LVDS for Low EMI
• Power down mode
• Low power single 3.3V CMOS design
• 100pin TQFP
• THC63LVDM83R compatible
   

Part Name(s) : NT5DS4M32EG NT5DS4M32EG-5G NT5DS4M32EG-5 NT5DS4M32EG-6 NANOAMP
NanoAmp Solutions, Inc.
Description : 1M × 32 Bits × 4 Banks Double Data Rate Synchronous RAM With Bi-Directional Data Strobe and DLL View

General Overview
The NT5DS4M32EG is 134,217,728 bits of double Data rate synchronous dynamic RAM organized as 4 x 1,048,576 bits by 32 I/Os. Synchronous features with Data Strobe allow extremely high performance up to 400Mbps/pin. I/O transactions are possible on both Edges of the clock. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.

Features
• VDD = 2.5V±5% , VDDQ = 2.5V±5%
• SSTL_2 compatible inputs/outputs
• 4 banks operation
• MRS cycle with address key programs
    -CAS latency 2,3 (clock)
    -Burst length (2, 4, 8 and Full page)
    -Burst type (sequential & interleave)
• Full page burst length for sequential burst type only
• Start address of the full page burst should be even
• All inputs except Data & DM are sampled at the Rising Edge of the system clock
• Differential clock input(CK & /CK)
Data I/O transaction on both Edges of Data Strobe
• 4 DQS (1 DQS/Byte)
• DLL aligns DQ and DQS transaction with Clock transaction
Edge aligned Data & Data Strobe output
• Center aligned Data & Data Strobe input
• DM for write masking only
• Auto & self refresh
• 32ms refresh period (4K cycle)
• 144-Ball FBGA package
• Maximum clock frequency up to 200MHz
• Maximum Data rate up to 400Mbps/pin

Part Name(s) : V386 V386G V386GLF V386GLFT V386GT ICST
Integrated Circuit Systems
Description : 8-BIT LVDS RECEIVER FOR VIDEO View

General Description
The V386 is an ideal LVDS receiver that converts 4-pair LVDS Data streams into parallel 28 bits of CMOS/TTL Data with bandwidth up to 2.38 Gbps throughput or 297.5 Mbytes per second.
This chip is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces through very low-swing LVDS signals.
ICS manufactures a large variety of video application devices. Consult ICS for all of your video application requirements.

Features
• Pin and function compatible with the National DS90CF386, THine THC63LVDF84, TI SN65LVDS94
• Converts 4-pair LVDS Data streams into parallel 28 bits of CMOS/TTL Data
• Fully spread spectrum compatible
• Wide clock frequency range from 20 MHz to 85 MHz
• Supports VGA, SVGA, XGA, and SXGA
LVDS voltage swing of 350 mV for low EMI
• On-chip PLL requires no external components
• Low-power CMOS design
• Falling Edge clock triggered outputs
• Power-down control function
• Compatible with TIA/EIA-644 LVDS standards
• Packaged in a 56-pin TSSOP (Pb free available)

 

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