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MC100LVEP14DTR2 Datasheet PDF - ON Semiconductor

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The MC100LVEP14 is a low skew 1−to−5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single−ended (if the VBB output is used). HSTL inputs can be used when the LVEP14 is operating under PECL conditions.
The LVEP14 specifically guarantees low output−to−output skew. Optimal design, layout, and processing minimize skew within a device and from device to device.
To ensure that the tight skew specification is realized, both sides of any differential output need to be terminated identically into 50 Ω even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew.

• 100 ps Device−to−Device Skew
• 25 ps Within Device Skew
• 400 ps Typical Propagation Delay
• Maximum Frequency > 2 GHz Typical
• The 100 Series Contains Temperature Compensation
• PECL and HSTL Mode:
   VCC = 2.375 V to 3.8 V with VEE = 0 V
• NECL Mode:
   VCC = 0 V with VEE = −2.375 V to −3.8 V
• LVDS Input Compatible
• Open Input Default State
• Pb−Free Packages are Available*


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