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DP80390 Datasheet PDF - Digital Core Design

Part NameDescriptionManufacturer
DP80390 Pipelined High Performance 8-bit Microcontroller DCD
Digital Core Design DCD
Other PDF  no available.
DP80390 Datasheet PDF : DP80390 pdf   
DP80390 image

OVERVIEW
DP80390 is an ultra high performance, speed optimized soft core of a single-chip 8-bit embedded controller dedicated for operation with fast (typically on-chip) and slow (off chip) memories. It supports up to 8 MB of linear code and 16 MB of linear data spaces. The core has been designed with a special concern about performance to power consumption ratio. This ratio is extended by an advanced power management unit PMU.
DP80390 soft core is 100% binary compatible with the industry standard 80390 & 8051 8-bit microcontrollers. There are two configurations of DP80390: Harward where internal data and program buses are separated, and von Neumann with common program and external data bus. DP80390 has Pipelined RISC architecture 10 times faster compared to standard architecture and executes 85-200 million instructions per second. This performance can also be exploited to great advantage in low power applications where the core can be clocked over ten times more slowly than the original implementation for no performance penalty.
DP80390 is delivered with fully automated testbench and complete set of tests allowing easy package validation at each stage of SoC design flow.

CPU FEATURES
● 100% software compatible with industry standard 80390 & 8051
   • LARGE mode – 8051 instruction set
   • FLAT mode – 80390 instruction set
● Pipelined RISC architecture enables to execute instructions 10 times faster compared to standard 8051
● 24 times faster multiplication
● 12 times faster addition
● Up to 256 bytes of internal (on-chip) Data Memory
● Up to 8M bytes of linear Program Memory
   • 64 kB of internal (on-chip) Program Memory
   • 8 MB external (off-chip) Program Memory
● Up to 16M bytes of external (off-chip) Data Memory
● User programmable Program Memory Wait States solution for wide range of memories speed
● User programmable External Data Memory Wait States solution for wide range of memories speed
● De-multiplexed Address/Data bus to allow easy connection to memory
● Dedicated signal for Program Memory writes.

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