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DAC34SH84 Datasheet PDF - Texas Instruments

Part NameDescriptionManufacturer
DAC34SH84 Quad-Channel, 16-Bit, 1.5 GSPS Digital-to-Analog Converter (DAC) Texas-Instruments
Texas Instruments Texas-Instruments
Other PDF  no available.
DAC34SH84 Datasheet PDF : DAC34SH84 pdf   
DAC34SH84 image

Description
The DAC34SH84 is a very low-power, high-dynamic range, quad-channel, 16-bit digital-to-analog converter (DAC) with a sample rate as high as 1.5 GSPS.
The device includes features that simplify the design of complex transmit architectures: 2× to 16× digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. Independent complex mixers allow flexible carrier placement.
A high-performance low-jitter clock multiplier simplifies clocking of the device without significant impact on the dynamic range. The digital quadrature modulator correction (QMC) enables complete IQ compensation for gain, offset and phase between channels in direct upconversion applications.
Digital data is input to the device through a 32-bit wide LVDS data bus with on-chip termination. The wide bus allows the processing of high-bandwidth signals. The device includes a FIFO, data pattern checker, and parity test to ease the input interface. The interface also allows full synchronization of multiple devices.
The device is characterized for operation over the entire industrial temperature range of –40°C to 85°C and is available in a 196-ball, 12-mm × 12-mm, 0.8-mm pitch NFBGA package.
The DAC34SH84 low-power, high-bandwidth support, superior crosstalk, high dynamic range, and features are an ideal fit for next-generation communication systems.

Features
• Low Power: 1.8 W at 1.5 GSPS, Full Operating
   Condition
• Multi-DAC Synchronization
• Selectable 2×, 4×, 8×, 16× Interpolation Filter
   – Stop-Band Attenuation > 90 dBc
• Flexible On-Chip Complex Mixing
   – Two Independent Fine Mixers With 32-Bit
      NCOs
   – Power-Saving Coarse Mixers: ±n × fS / 8
• High-Performance, Low-Jitter Clock-Multiplying
   PLL
• Digital I and Q Correction
   – Gain, Phase and Offset
• Digital Inverse Sinc Filters
• 32-Bit DDR Flexible LVDS Input Data Bus
   – 8-Sample Input FIFO
   – Supports Data Rates up to 750 MSPS
   – Data Pattern Checker
   – Parity Check
• Temperature Sensor
• Differential Scalable Output: 10 mA to 30 mA
• 196-Ball, 12-mm × 12-mm NFBGA

Applications
• Cellular Base Stations
• Diversity Transmit
• Wideband Communications

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