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DAC34H84 Datasheet PDF - Texas Instruments

Part NameDescriptionManufacturer
DAC34H84 Quad-Channel, 16-Bit, 1.25 GSPS Digital-to-Analog Converter (DAC) Texas-Instruments
Texas Instruments Texas-Instruments
Other PDF  no available.
DAC34H84 Datasheet PDF : DAC34H84 pdf   
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Description
The DAC34H84 is a very low power, high dynamic range, quad-channel, 16-bit digital-to-analog converter (DAC) with a sample rate as high as 1.25 GSPS.
The device includes features that simplify the design of complex transmit architectures: 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. Independent complex mixers allow flexible carrier placement.
A high-performance low jitter clock multiplier simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) enables complete IQ compensation for gain, offset, phase and group delay between channels in direct up-conversion applications.
Digital data is input to the device through a 32-bit wide LVDS data bus with on-chip termination. The wide bus allows the processing of very high bandwidth signals. The device includes a FIFO, data pattern checker and parity test to ease the input interface. The interface also allows full synchronization of multiple devices.
The device is characterized for operation over the entire industrial temperature range of –40°C to 85°C and is available in a 196-ball, 12x12mm, 0.8mm pitch BGA package.
The DAC34H84 very low power, high bandwidth support, superior crosstalk, high dynamic range and features are an ideal fit for next generation communication systems.

Features
• Very Low Power: 1.4 W at 1.25 GSPS
• Multi-DAC Synchronization
• Selectable 2x, 4x, 8x, 16x Interpolation Filter
   – Stop-Band Attenuation > 90 dBc
• Flexible On-chip Complex Mixing
   – Two Independent Fine Mixers with 32-bit
      NCOs
   – Power Saving Coarse Mixers: ± n×Fs/8
• High Performance, Low Jitter Clock Multiplying
   PLL
• Digital I and Q Correction
   – Gain, Phase, Offset, and Group Delay
      Correction
• Digital Inverse Sinc Filters
• 32-Bit DDR Flexible LVDS Input Data Bus
   – 8 Sample Input FIFO
   – Supports Data Rates up to 625 MSPS
   – Data Pattern Checker
   – Parity Check
• Temperature Sensor
• Differential Scalable Output: 10mA to 30mA
• 196-Ball, 12x12mm NFBGA (GREEN / Pb-Free)

Applications
• Cellular Base Stations
• Diversity Transmit
• Wideband Communications

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