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DAC3482 Datasheet PDF - Texas Instruments

Part NameDescriptionManufacturer
DAC3482 Dual-Channel, 16-Bit, 1.25 GSPS Digital-to-Analog Converter (DAC) Texas-Instruments
Texas Instruments Texas-Instruments
Other PDF  no available.
DAC3482 Datasheet PDF : DAC3482 pdf   
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Description
The DAC3482 is a very low power, high dynamic range, dual-channel, 16-bit digital-to-analog converter (DAC) with a sample rate as high as 1.25 GSPS.
The device includes features that simplify the design of complex transmit architectures: 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. A complex mixer allows flexible carrier placement. A high-performance low jitter clock multiplier simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) enables complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications.
Digital data is input to the device through a flexible LVDS data bus with on-chip termination. Data can be input either word-wide or byte-wide. The device includes a FIFO, data pattern checker and parity test to ease the input interface. The interface also allows full synchronization of multiple devices.
The device is characterized for operation over the entire industrial temperature range of –40°C to 85°C and is available in a very-small 88-pin 9x9mm WQFN-MR package or 196-ball 12x12mm NFBGA package.
Very low power, small size, superior crosstalk, high dynamic range, and features of the DAC3482 make it an ideal fit for today’s communication systems.

Features
• Very Low Power: 900 mW at 1.25 GSPS, Full
   Operating Conditions
• Multi-DAC Synchronization
• Selectable 2x, 4x, 8x, 16x Interpolation Filter
   – Stop-Band Attenuation > 90 dBc
• Flexible On-Chip Complex Mixing
   – Fine Mixer with 32-Bit NCO
   – Power Saving Coarse Mixer: ± n×Fs/8
• High Performance, Low Jitter Clock Multiplying
   PLL
• Digital I and Q Correction
   – Gain, Phase, Offset, and Group Delay
      Correction
• Digital Inverse Sinc Filter
• Flexible LVDS Input Data Bus
   – Word- or Byte-Wide Interface
   – 8 Sample Input FIFO
   – Data Pattern Checker
   – Parity Check
• Temperature Sensor
• Differential Scalable Output: 10 mA to 30 mA
• Multiple Package Options: 88-Pin 9x9mm WQFN-
   MR and 196-ball 12mmx12mm NFBGA (GREEN / Pb-Free)

Applications
• Cellular Base Stations
• Diversity Transmit
• Wideband Communications

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