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AM29LV200BT55REC Datasheet PDF - Advanced Micro Devices

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AM29LV200BT55REC Datasheet PDF : AM29LV200BT55REC pdf     
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The Am29LV200B is a 2 Mbit, 3.0 volt-only Flash memory organized as 262,144 bytes or 131,072 words. The device is offered in 44-pin SO, 48-pin TSOP, and 48-ball FBGA packages. The word-wide data (x16) appears on DQ15-DQ0; the byte-wide (x8) data appears on DQ7-DQ0. This device is designed to be programmed in-system using only a single 3.0 volt VCC supply. No VPP is required for write or erase operations. The device can also be programmed in standard EPROM programmers.

■ Single power supply operation
    — 2.7 to 3.6 volt read and write operations for battery-powered applications
■ Manufactured on 0.32 µm process technology
    — Compatible with 0.5 µm Am29LV200 device
■ High performance
    — Full voltage range: access times as fast as 70 ns
    — Regulated voltage range: access times as fast as 55 ns
■ Ultra low power consumption (typical values at 5 MHz)
    — 200 nA Automatic Sleep mode current
    — 200 nA standby mode current
    — 7 mA read current
    — 15 mA program/erase current
■ Flexible sector architecture
    — One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and three 64 Kbyte sectors (byte mode)
    — One 8 Kword, two 4 Kword, one 16 Kword, and three 32 Kword sectors (word mode)
    — Supports full chip erase
    — Sector Protection features:
        A hardware method of locking a sector to prevent any program or erase operations within that sector
        Sectors can be locked in-system or via programming equipment
        Temporary Sector Unprotect feature allows code changes in previously locked sectors
■ Unlock Bypass Program Command
    — Reduces overall programming time when issuing multiple program command sequences
■ Top or bottom boot block configurations available
■ Embedded Algorithms
    — Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors
    — Embedded Program algorithm automatically writes and verifies data at specified addresses
■ Minimum 1 million erase cycle guarantee per sector
■ 20-year data retention at 125°C
    — Reliable operation for the life of the system
■ Package option
    — 48-pin TSOP
    — 44-pin SO
    — 48-ball FBGA
■ Compatibility with JEDEC standards
    — Pinout and software compatible with singlepower supply Flash
    — Superior inadvertent write protection
■ Data# Polling and toggle bits
    — Provides a software method of detecting program or erase operation completion
■ Ready/Busy# pin (RY/BY#)
    — Provides a hardware method of detecting program or erase cycle completion
■ Erase Suspend/Erase Resume
    — Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation
■ Hardware reset pin (RESET#)
    — Hardware method to reset the device to reading array data


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